Commit graph

13044 commits

Author SHA1 Message Date
Samuel Pitoiset
17cd153dd0 radv: add support for DGC with SQTT
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
2023-09-06 07:52:50 +00:00
Samuel Pitoiset
63e0fcfb13 radv: avoid emitting SQTT markers for DGC calls
This confuses RGP.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25035>
2023-09-06 07:52:50 +00:00
Chris Spencer
9123505dde radv/video: use correct enum value for max level IDC
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24649>
2023-09-06 05:10:33 +00:00
Marek Olšák
3040aa2e26 ac/llvm: don't convert undef to 0 because nir_opt_undef does it now
TOTALS FROM AFFECTED SHADERS (29663/58918)
  Code Size: 39163724 -> 37842360 (-3.37 %) bytes
  Max Waves: 394813 -> 396334 (0.39 %)
  Outputs: 84616 -> 84616 (0.00 %)
  Patch Outputs: 0 -> 0 (0.00 %)

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24059>
2023-09-06 03:24:16 +00:00
antonino
aa657247ce vulkan/wsi: add vk_wsi_force_swapchain_to_current_extent driconf
Add a driconf to force the swapchain size to match
`VkSurfaceCapabilities2KHR::currentExtent` as a workaround for
misbehaved games

Fixes: 6139493ae3 ("vulkan/wsi: return VK_SUBOPTIMAL_KHR for sw/x11 on window resize")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24818>
2023-09-06 00:10:41 +00:00
Samuel Pitoiset
e80fddf81f radv/amdgpu: do not copy the original chain link for IBs
Otherwise, if a secondary CS is grown and then executed without IB2,
the INDIRECT_BUFFER packet would have been copied but it shouldn't.

This fixes a regression that introduced GPU hangs with
gl_vk_meshlet_cadscene on RDNA2.

Fixes: df0c742543 ("radv/amdgpu: rework growing a CS with the chained IB path slightly")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
2023-09-05 12:38:33 +00:00
Samuel Pitoiset
9206aeb077 radv/amdgpu: fix executing secondaries without IB2
If a secondary cmdbuf has been grown and is executed without IB2
(eg. on compute queue or when it's not allowed), the ib size ptr
contains chaining info, which means the IB size was wrong.

This fixes CPU crashes when running gl_vk_meshlet_cadscene.

Fixes: 277b2afd70 ("radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
2023-09-05 12:38:33 +00:00
Samuel Pitoiset
4a8afc9072 radv/ci: re-enable vkd3d-polaris10-valve
Like the vkcts job, this was disabled a while ago but it seems to be
working well again.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25025>
2023-09-04 16:56:34 +00:00
Samuel Pitoiset
083e7d3a92 radv: fix capturing indirect dispatches with SQTT
Looks like indirect dispatches require an event marker instead of an
event marker with dims. That makes sense somehow given the blocks size
is not known at record time with indirect dispatches.

This allows RGP to report correct block sizes.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24994>
2023-09-04 06:31:40 +00:00
Qiang Yu
b5eaec6c80 aco,radv,radeonsi: rename is_monolithic to merged_shader_compiled_separately
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24990>
2023-09-04 10:53:44 +08:00
Timur Kristóf
19a7d9615c ac/nir/ngg: Extract nogs_export_vertex_params function.
Just for better code readability. No functional changes.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
2023-09-03 11:04:35 +00:00
Timur Kristóf
93b4f200de ac/nir/ngg: Wait for attribute ring stores in mesh shaders.
Make sure that both per-vertex and per-primitive attribute
ring stores are finished before position or primitive export
instructions are executed.

This is necessary because we need to ensure that mesh shader
waves work correctly when they have either vertex-only or
primitive-only waves.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
2023-09-03 11:04:35 +00:00
Timur Kristóf
0721784b78 ac/nir/ngg: Refactor mesh shader primitive export.
Cleanup the code that generates the two channels of the
primitive export instruction, and move storing the built-in
per-primitive outputs out to match how vertex attributes work.

Prepares the mesh shader lowering for a workaround that
affect export instructions.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
2023-09-03 11:04:35 +00:00
Timur Kristóf
edd51655f0 ac/nir/ngg: Wait for attribute stores before VS/TES/GS pos0 export.
This is a HW bug workaround for some (all?) GFX11 chips.

On these chips, rasterization can start before the attribute ring
stores are finished, which can cause issues.
As a workaround, wait for attribute ring stores to finish
before doing the position export.

Mesh shaders will be taken care of in another commit.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
2023-09-03 11:04:35 +00:00
Timur Kristóf
9c096e4ace ac/nir: Slightly refactor how pos0 exports are added when missing.
Prepares for a workaround. Makes it possible for this function
to not emit the pos0 export at all so that it can be emitted
by a subsequent call to the function later.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
2023-09-03 11:04:35 +00:00
Timur Kristóf
838d886d90 ac/nir: Add done arg to ac_nir_export_position.
This prepares for a workaround where we won't need to add
the done flag to the last export in this function, because
it will be added in a subsequent call to the same function.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
2023-09-03 11:04:35 +00:00
Georg Lehmann
2ae94b3894 aco: implement some exclusive scans with inclusive scans
exclusive scan lowering uses full wave shift, for iadd/ixor it's faster
to do inclusive scans and subtract/xor the thread's source.

Foz-DB Navi21:
Totals from 21 (0.02% of 132657) affected shaders:
Instrs: 10925 -> 10727 (-1.81%)
CodeSize: 58064 -> 56488 (-2.71%)
Latency: 178471 -> 177928 (-0.30%)
InvThroughput: 24374 -> 24145 (-0.94%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24555>
2023-09-02 11:42:22 +00:00
Georg Lehmann
bce9bba90d nir: add nir_scalar intrinsic helpers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
2023-09-02 00:26:31 +00:00
Eric Engestrom
a8c7a2fb69 ci/amd: split the polaris10 rules into one for each farm
There is now one polaris10 in each farm, so we need two rules for which
one to use.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24996>
2023-09-01 19:35:33 +00:00
Georg Lehmann
cda5784eb3 aco: use v_cvt_f32_ubyte for signed casts too
The extract is always positive, so signed vs unsigned conversion doesn't matter.

Foz-DB GFX11:
Totals from 167 (0.13% of 133461) affected shaders:
Instrs: 401631 -> 401225 (-0.10%)
CodeSize: 2107256 -> 2104344 (-0.14%)
VGPRs: 13320 -> 13332 (+0.09%)
Latency: 6468063 -> 6467241 (-0.01%)
InvThroughput: 801854 -> 801653 (-0.03%)
Copies: 13926 -> 13927 (+0.01%); split: -0.08%, +0.09%

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24893>
2023-09-01 17:21:57 +00:00
Samuel Pitoiset
223d00fe0a radv/ci: re-enable vkcts-polaris10-valve
This was disabled a long time ago because of unknown GPU hangs during
boot but it seems stable again for some reasons.

This also bumps the job timeouts to make sure it will be able to finish.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24968>
2023-09-01 15:14:58 +00:00
Tapani Pälli
48a41c7700 ci: add a fix for KHR-GLES3.packed_pixels.*snorm tests
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24600>
2023-09-01 10:37:43 +00:00
Konstantin Seurer
0385dcac5c aco/lower_to_cssa: Fix typo
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
2023-09-01 07:23:33 +00:00
Konstantin Seurer
ce4c38ecae radv: Only generate debug info if required
Fixes: 51f2fa1a5e ("radv: Break up radv_shader_nir_to_asm")
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
2023-09-01 07:23:33 +00:00
Konstantin Seurer
2a5d8d4cf4 aco: Unify demote and demote_if selection
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
2023-09-01 07:23:33 +00:00
Konstantin Seurer
9af91edda9 aco: Use bytes() instead of size() in emit_wqm
This should get most of the cases that would fail validation.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
2023-09-01 07:23:33 +00:00
Konstantin Seurer
1ddf8378cb aco/validate: Handle p_wqm like p_parallelcopy
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24906>
2023-09-01 07:23:32 +00:00
Samuel Pitoiset
e104718c9f aco: allow separate compilation of NGG shaders
Also prevent to emit a long-jump for VS as NGG without a GS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
2023-09-01 06:52:40 +00:00
Samuel Pitoiset
ee8ba0f98f aco: adjust fix_exports() for VS/TES as NGG and non-monolithic shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
2023-09-01 06:52:40 +00:00
Samuel Pitoiset
bfb39031f1 aco: flag blocks with long-jump as export_end for separate compilation
This will allow us to adjust fix_exports().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
2023-09-01 06:52:40 +00:00
Samuel Pitoiset
05185e8412 radv: preserve shader argument for separate compilation of NGG shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24907>
2023-09-01 06:52:40 +00:00
Lang Yu
11106bab1b amd/common: add AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32 property
This property can be used to determine wave size on gfx10+.

Signed-off-by: Lang Yu <lang.yu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24920>
2023-08-31 20:30:03 +00:00
Friedrich Vock
728f6c0b70 radv/rt: Pre-initialize instance address
It's not disallowed by spec to load instance-related data in case of a
miss where no instance was ever visited. Such loads make no sense, so we
can return garbage, but it mustn't hang the GPU. Initialize the instance
addresses to the TLAS base to make sure we always have valid memory to load from.

Partially fixes GPU hangs in RTX Remix games.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24971>
2023-08-31 16:29:52 +00:00
Qiang Yu
c8687a4b09 aco: do not fix_exports when program is prolog
Otherwise fix_export() will abort when find no export.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>
2023-08-31 02:39:16 +00:00
Qiang Yu
9cce7ce80a aco: add aco compile interface for radeonsi vs prolog
Radeonsi prolog does not need s_endpgm.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>
2023-08-31 02:39:16 +00:00
Qiang Yu
a2ba50aee6 aco: add vs prolog instruction selection for radeonsi
Port from llvm si_llvm_build_vs_prolog().

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>
2023-08-31 02:39:15 +00:00
Qiang Yu
3f87413811 aco: prepare fix_ls_vgpr_init_bug to be used by gl vs prolog
Prolog does not have nir shader.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>
2023-08-31 02:39:15 +00:00
Qiang Yu
eb4f871034 aco: pass sw_stage when setup_isel_context
We are going to add more shader parts.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>
2023-08-31 02:39:15 +00:00
Qiang Yu
ffd7328547 aco: simplify setup_tcs_info
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24712>
2023-08-31 02:39:15 +00:00
Alyssa Rosenzweig
8efc25c54c radv: Use before/after_cf_list for entrypoints
Via Coccinelle patch:

    @@
    expression shader;
    @@

    -nir_before_cf_list(&nir_shader_get_entrypoint(shader)->body)
    +nir_before_impl(nir_shader_get_entrypoint(shader))

    @@
    expression shader;
    @@

    -nir_after_cf_list(&nir_shader_get_entrypoint(shader)->body)
    +nir_after_impl(nir_shader_get_entrypoint(shader))

Suggested-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>
2023-08-30 19:30:58 +00:00
Alyssa Rosenzweig
25cc04c59b treewide: Use nir_before/after_impl in easy cases
These open-code the same idiom as the helper.

Via Coccinelle patch:

    @@
    expression func_impl;
    @@

    -nir_before_cf_list(&func_impl->body)
    +nir_before_impl(func_impl)

    @@
    expression func_impl;
    @@

    -nir_after_cf_list(&func_impl->body)
    +nir_after_impl(func_impl)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24910>
2023-08-30 19:30:58 +00:00
Samuel Pitoiset
088c2bbd51 amd/ci: update list of failures/flakes for glcts-vangogh-valve
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24952>
2023-08-30 15:46:34 +00:00
Rhys Perry
c7bb2f7bb9 aco/spill: add all live-in to merge block spill candidates
Previously, only already spilled live-in or phis were added to the spill
candidates. Because of branch definitions, this might not be enough.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9722
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24949>
2023-08-30 15:20:02 +00:00
Simon Ser
6c469f9b19 radv/winsys: check amdgpu_create_bo_from_user_mem() for EINVAL
amdgpu_create_bo_from_user_mem() may fail for multiple reasons.
Only return VK_ERROR_INVALID_EXTERNAL_HANDLE if the kernel
returned EINVAL, which indicates a bad input parameter.

Signed-off-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24858>
2023-08-30 09:42:05 +00:00
Samuel Pitoiset
496a17bffe radv: re-order IO slot layout for stages that aren't linked
Otherwise, if eg. PSIZ is exported the ESGS stride is wrong. This isn't
optimal yet but let's start with this to support separate compilation
of VS/TCS/TES/GS correctly first.

This fixes a bunch of issues when forcing separate compilation on RDNA2.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24908>
2023-08-30 08:59:06 +00:00
Karol Herbst
a19f98a134 ac: drop 64 bit handling for cl workgroup intrinsics
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>
2023-08-30 07:04:33 +00:00
Karol Herbst
513cd29eda nir: make num_workgroups 32 bit only
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>
2023-08-30 07:04:33 +00:00
Karol Herbst
1b22b67199 nir: make workgroup_id 32 bit only
No backend supports 64 bit values natively anyway.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24905>
2023-08-30 07:04:33 +00:00
Rhys Perry
cb096b85ff aco/spill: skip p_branch in process_block
Fixes compilation of a Dead by Daylight shader.

fossil-db (gfx1100):
Totals from 58 (0.04% of 133461) affected shaders:
Instrs: 319824 -> 319421 (-0.13%); split: -0.13%, +0.00%
CodeSize: 1711260 -> 1708744 (-0.15%); split: -0.15%, +0.00%
SpillSGPRs: 2567 -> 2459 (-4.21%)
Latency: 3274930 -> 3274921 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 924106 -> 924105 (-0.00%); split: -0.00%, +0.00%
Copies: 41883 -> 41757 (-0.30%); split: -0.31%, +0.00%
Branches: 9144 -> 9146 (+0.02%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9599
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24896>
2023-08-29 11:53:57 +00:00
Samuel Pitoiset
f30d47c518 aco: fix emitting TCS epilogs end on GFX9+
With merged shaders, the long-jump should be emitted inside the
divergent if (ie. only for TCS invocations) and other non TCS
invocations should just end the program.

This fixes a bunch of failures with CTS by forcing TCS epilogs on
RDNA2.

Not sure how RadeonSI will handle that but maybe doing the merged
wave info thing in epilogs would help.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24832>
2023-08-29 09:30:07 +00:00