It's allowed to place OpExecuteCallableKHR in a SPIR-V, even if the RT
pipeline doesn't contain any callable shaders. Unreal hits this case and
crashes. We can assume the intrinsic never gets executed, so we can
simply remove it.
Cc: mesa-stable
(cherry picked from commit 0c02a7e8e8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
The current assertion fails as soon as a MAD with src0 and src2 being
immediate is detected.
The assertion was supposted to catch, "If it's ADD3, only one of src0
and src2 can be immediate." The detect this, the opcode test should have
been !=.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: c1c09e3c4a ("brw/emit: Add correct 3-source instruction assertions for each platform")
(cherry picked from commit c52ce6157f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Some callers of brw_constant_fold_instruction depend on the result being
a MOV of immediate when progress is made. Previously `MUL dst:D src0:D
1:D` would be converted to `MOV dst:D src0:D`. There was also no
handling for `MUL dst:D imm0:D imm1:D`.
This could cause problems if one of the immedate values was -1. The
existing code would convert this to a `MOV dst:D imm0:D` and set the
negate flag on src0. That is not correct.
v2: Fix the is_negative_one case handling of the non-negative-one
source. Add a comment explaining the assertion. Both suggested by Caio.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 2cc1575a31 ("brw/algebraic: Refactor constant folding out of brw_fs_opt_algebraic")
(cherry picked from commit 25de9dcd76)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Some callers of brw_constant_fold_instruction depend on the result being
a MOV of immediate when progress is made. Previously `ADD dst:D src0:D
0:D` would be converted to `MOV dst:D src0:D`. There was also no
handling for `ADD dst:D imm0:D imm1:D`.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 2cc1575a31 ("brw/algebraic: Refactor constant folding out of brw_fs_opt_algebraic")
(cherry picked from commit 086e83ccd9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
In this case, num_sources is bigger than this->sources, so if we loop
up to num_sources (instead of this->sources) we'll end up reading past
the end of old_src[]. Only copy up to what we originally had.
This was found by code inspection, I'm not aware of any applications
failing due to the lack of this patch.
Fixes: d9e737212d ("intel/brw: Add a src array for the common case in fs_inst")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(cherry picked from commit d4a54d4f92)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Rather than checking hwconfig items when using them, wait until after
devinfo has been fully initialized. This includes having workarounds
implemented.
We can then check if the hwconfig data and final Mesa initialization
agree. If the match fails, we need to investigate if Mesa or the
hwconfig data is wrong.
This code becomes a no-op when not on a release build.
Fixes: a4c5bfd34c ("intel/dev: Use hwconfig for urb min/max entry values")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12141
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 1027b071f9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Water puddles expect invariant position, but does not declare such in
the vertex shaders, leading to random glitches.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit e815d6523c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Displayable DCC should also be disabled, otherwise it's asserting
somewhere in ac_surface.c
Fixes: e3d1f27b31 ("radv: add radv_disable_dcc_stores and enable for Indiana Jones: The Great Circle")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 4d1aa9a2d0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Likely a game bug but can't be 100% sure because the game uses RT by
default and renderdoc still doesn't have support for it.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit e3d1f27b31)
Conflicts:
src/util/00-radv-defaults.conf
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Unscissored glClearColor is using i915_fill_blit().
Clearing can be done with the 1 byte formats
GL_ALPHA, GL_LUMINANCE or GL_INTENSITY.
Routine i915_fill_blit() is called with a rgba-mask containing
1 byte, but it is handling this as a 2-byte color.
This fix adds the needed 1 byte setup to both
i915_fill_blit() and i915_copy_blit().
It solves 1 piglit-test concerning arb_clear_texture-base-formats
and 15 tests concerning fbo-clear-formats.
No regression is shown at other piglit-tests.
Cc: mesa-stable
Signed-off-by: GKraats <vd.kraats@hccnet.nl>
(cherry picked from commit bed66430ab)
Conflicts:
src/gallium/drivers/i915/ci/i915-g33-fails.txt
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
VRS rates should only be preserved for clears, otherwise the HTILE
buffer should be cleared completely.
This fixes some failures/flakes in CI.
Fixes: 8197d744f5 ("radv: Do not overwrite VRS rates when doing fast clears")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 8b755840fc)
Conflicts:
src/amd/vulkan/meta/radv_meta_clear.c
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
In the very unlikely case that the packed AFBC image will not
save (enough) memory, we abort packing. In this case we should
free the BO associated with the metadata.
Fixes: 5a928f7563 ("panfrost: Add env variable for max AFBC packing ratio")
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit f8bc6c8663)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
We read the source rather than write it, due to a typo we were
not setting this correctly though.
Fixes: bc55d150a9 ("panfrost: Add support for AFBC packing")
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
(cherry picked from commit b59e73e426)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
The override used for the immed encoding in #cat3-src-const-or-immed
used a pattern which isn't supported in overrides by isaspec. The
pattern in the base bitset (10) was too strict for immediates since it
didn't allow the most significant bit to be 1.
Fix this by making the base pattern 1 and adding an assert for the next
bit to be 0 in the non-immed case.
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 1c6c200c0d ("ir3: add newly found shlg.b16 instruction")
(cherry picked from commit 943f666b69)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
ttmp sgprs are readonly outside of trap handlers, so the instructions were
probably skipped. RA should also never create additional exec writes.
Fixes: e06773281b ("aco/ra: Optimize some SOP2 instructions with literal to SOPK.")
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
(cherry picked from commit fe0c72caec)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
When a timestamped present is not used (MAILBOX or the very first present),
it's possible that the very last queued present ID won't complete in finite time.
Similar to frame callback based workaround, apply a timeout to present
waits when they target the very last submitted presentID.
Only apply the workaround when we're not guaranteed forward progress.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Derek Foreman <derek.foreman@collabora.com>
(cherry picked from commit c3becade15)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
When transitioning from FIFO to MAILBOX with swapchain_maintenance1,
we must make sure that the first MAILBOX after FIFO observes the wait
barrier. This was done implicitly in the timestamp path, but not for
the non-commit-timing path.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Cc: mesa-stable
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Derek Foreman <derek.foreman@collabora.com>
(cherry picked from commit 63cbbf2a1c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
When commit-timing was not supported, but FIFO was we would end
up in a situation with throttling on FIFO barrier and legacy fence.
At that point, the entire point of FIFO falls flat.
There are some caveats with this approach, but it's not expected
that compositors will only support FIFO, and not commit-timing long
term.
Signed-off-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Fixes: c26ab1aee1 ("vulkan/wsi/wayland: Pace frames with commit-timing-v1")
Reviewed-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Derek Foreman <derek.foreman@collabora.com>
(cherry picked from commit 458842c3b5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Right now the driver doesn't support multi-slice encodes, so
report the correct value.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Autumn Ashton
Cc: mesa-stable
(cherry picked from commit 699afb88ec)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Currently `util_idalloc_foreach()` isn't being used in the codebase
but if used it causes a build error as `num_used` doesn't exist.
Fix that by using `num_set_elements`.
Fixes: 0589dfe4e2 ("util/idalloc: optimize foreach by tracking the greatest non-zero element")
Signed-off-by: Karmjit Mahil <karmjit.mahil@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
(cherry picked from commit af346cd77f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
The last argument seems to be used as brw_shader_reloc::delta (from
brw_add_reloc), and we're unconditionally setting it to 0 here, while
the other place where we handle nir_intrinsic_load_reloc_const_intel
seems to be setting the base appropriately.
I found this by inspection while debugging a bug related to this code,
so I'm not aware of any workloads that get improved by this patch.
Related patches:
- ecbec25e84 ("intel/nir: add reloc delta to load_reloc_const_intel intrinsic")
- 99047451c9 ("intel/fs: add plumbing for embedded samplers")
Fixes: ecbec25e84 ("intel/nir: add reloc delta to load_reloc_const_intel intrinsic")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
(cherry picked from commit 0dc2a5808e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
Real Xe KMD actually returns a uint64, so here changing from uint32
to uint64.
Fixes: 04bdbeec31 ("intel/dev/xe: Fix access to eu_per_dss_mask")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 2aae000edb)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
DRM_XE_TOPO_EU_PER_DSS and DRM_XE_TOPO_SIMD16_EU_PER_DSS can be any
number of bytes long but it was assuming it was always 4 bytes long.
That was not a issue because Xe KMD return 4 bytes even if only needs
1 or 2 bytes but that is a problem with our HW simulator that was
returning 2 bytes.
Fixes: a24d93aa89 ("intel/dev: Query and compute hardware topology for Xe")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 04bdbeec31)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
These shaders are created using nir_builder_init_simple_shader(), which
allocates using a NULL ralloc-parent, so ralloc_free should be the right
function to free them with.
Fixes: 0bc3502ca3 ("panvk: Implement a custom FB preload logic")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
(cherry picked from commit 9f69f7a66d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
We create NIR shaders here, and we need to free them when we're done with
them as well.
These shaders are created using nir_builder_init_simple_shader(), which
allocates using a NULL ralloc-parent, so ralloc_free should be the right
function to free them with.
Fixes: 514c10344e ("vulkan/meta: Add a concept of rect pipelines")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
(cherry picked from commit 43738a9a94)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
This was just broken because individual shaders were still stored
on-disk in many situations:
- for shader object, all compute/graphics shaders were stored
- for fast-GPL, graphics shaders were stored
- for pipeline binaries, when the create flag was used
- for rt capture/replay and ray history
This should stop storing unused binaries on-disk and save space.
Found this by inspection.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32476>
