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anv: Enable MCS_CCS compression on Gfx12+

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Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10971
(cherry picked from commit fef8490eb9)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32730>
This commit is contained in:
Sagar Ghuge 2024-11-02 06:50:02 -07:00 • committed by Marge Bot
parent 54adfc351f
commit 77248fa11f
3 changed files with 25 additions and 6 deletions
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2
src/intel/vulkan/anv_blorp.c
View file

@ -1367,7 +1367,7 @@ exec_mcs_op(struct anv_cmd_buffer *cmd_buffer,
struct blorp_surf surf;
get_blorp_surf_for_anv_image(cmd_buffer, image, aspect,
0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
ISL_AUX_USAGE_MCS, format, &surf);
image->planes[0].aux_usage, format, &surf);
/* Blorp will store the clear color for us if we provide the clear color
* address and we are doing a fast clear. So we save the clear value into

27
src/intel/vulkan/anv_image.c
View file

@ -900,13 +900,27 @@ add_aux_surface_if_supported(struct anv_device *device,
if (!ok)
return VK_SUCCESS;
image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
if (isl_surf_supports_ccs(&device->isl_dev,
&image->planes[plane].primary_surface.isl,
&image->planes[plane].aux_surface.isl)) {
image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS_CCS;
} else {
image->planes[plane].aux_usage = ISL_AUX_USAGE_MCS;
}
result = add_surface(device, image, &image->planes[plane].aux_surface,
binding, ANV_OFFSET_IMPLICIT);
if (result != VK_SUCCESS)
return result;
if (anv_image_plane_uses_aux_map(device, image, plane)) {
result = add_compression_control_buffer(device, image, plane,
binding,
ANV_OFFSET_IMPLICIT);
if (result != VK_SUCCESS)
return result;
}
if (device->info->ver <= 12)
return add_aux_state_tracking_buffer(device, image, aux_state_offset,
plane);
@ -2818,9 +2832,12 @@ anv_bind_image_memory(struct anv_device *device,
anv_perf_warn(VK_LOG_OBJS(&image->vk.base),
"BO lacks CCS support. Disabling the CCS aux usage.");
if (image->planes[p].aux_surface.memory_range.size > 0) {
assert(image->planes[p].aux_usage == ISL_AUX_USAGE_HIZ_CCS ||
image->planes[p].aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT);
if (image->planes[p].aux_usage == ISL_AUX_USAGE_MCS_CCS) {
assert(image->planes[p].aux_surface.memory_range.size);
image->planes[p].aux_usage = ISL_AUX_USAGE_MCS;
} else if (image->planes[p].aux_usage == ISL_AUX_USAGE_HIZ_CCS ||
image->planes[p].aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
assert(image->planes[p].aux_surface.memory_range.size);
image->planes[p].aux_usage = ISL_AUX_USAGE_HIZ;
} else {
assert(image->planes[p].aux_usage == ISL_AUX_USAGE_CCS_E ||
@ -3239,6 +3256,7 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
break;
case ISL_AUX_USAGE_MCS:
case ISL_AUX_USAGE_MCS_CCS:
if (!anv_can_sample_mcs_with_clear(devinfo, image))
clear_supported = false;
break;
@ -3287,6 +3305,7 @@ anv_layout_to_aux_state(const struct intel_device_info * const devinfo,
}
case ISL_AUX_USAGE_MCS:
case ISL_AUX_USAGE_MCS_CCS:
assert(aux_supported);
if (clear_supported) {
return ISL_AUX_STATE_COMPRESSED_CLEAR;

2
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -1150,7 +1150,7 @@ transition_color_buffer(struct anv_cmd_buffer *cmd_buffer,
*/
must_init_fast_clear_state = devinfo->ver < 20;
if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS ||
if (isl_aux_usage_has_mcs(image->planes[plane].aux_usage) ||
devinfo->has_illegal_ccs_values) {
must_init_aux_surface = true;