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intel/dev: Query and compute hardware topology for Xe
Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21368>
This commit is contained in:
José Roberto de Souza
Marge Bot
parent
4b81a80f55
commit
a24d93aa89
1 changed files with 138 additions and 0 deletions
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@ -155,6 +155,141 @@ xe_query_hwconfig(int fd, struct intel_device_info *devinfo)
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return ret;
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}
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static void
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xe_compute_topology(struct intel_device_info * devinfo,
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const uint8_t *geo_dss_mask,
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const uint32_t geo_dss_num_bytes,
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const uint32_t *eu_per_dss_mask)
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{
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intel_device_info_topology_reset_masks(devinfo);
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/* TGL/DG1/ADL-P: 1 slice x 6 dual sub slices
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* RKL/ADL-S: 1 slice x 2 dual sub slices
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* DG2: 8 slices x 4 dual sub slices
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*/
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if (devinfo->verx10 >= 125) {
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devinfo->max_slices = 8;
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devinfo->max_subslices_per_slice = 4;
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} else {
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devinfo->max_slices = 1;
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devinfo->max_subslices_per_slice = 6;
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}
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devinfo->max_eus_per_subslice = 16;
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devinfo->subslice_slice_stride = 1;
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devinfo->eu_slice_stride = DIV_ROUND_UP(16 * 4, 8);
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devinfo->eu_subslice_stride = DIV_ROUND_UP(16, 8);
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assert((sizeof(uint32_t) * 8) >= devinfo->max_subslices_per_slice);
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assert((sizeof(uint32_t) * 8) >= devinfo->max_eus_per_subslice);
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const uint32_t dss_mask_in_slice = (1u << devinfo->max_subslices_per_slice) - 1;
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struct slice {
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uint32_t dss_mask;
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struct {
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bool enabled;
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uint32_t eu_mask;
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} dual_subslice[INTEL_DEVICE_MAX_SUBSLICES];
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} slices[INTEL_DEVICE_MAX_SLICES] = {};
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/* Compute and fill slices */
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for (unsigned s = 0; s < devinfo->max_slices; s++) {
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const unsigned first_bit = s * devinfo->max_subslices_per_slice;
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const unsigned dss_index = first_bit / 8;
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const unsigned shift = first_bit % 8;
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assert(geo_dss_num_bytes > dss_index);
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const uint32_t *dss_mask_ptr = (const uint32_t *)&geo_dss_mask[dss_index];
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uint32_t dss_mask = *dss_mask_ptr;
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dss_mask >>= shift;
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dss_mask &= dss_mask_in_slice;
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if (dss_mask) {
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slices[s].dss_mask = dss_mask;
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for (uint32_t dss = 0; dss < devinfo->max_subslices_per_slice; dss++) {
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if ((1u << dss) & slices[s].dss_mask) {
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slices[s].dual_subslice[dss].enabled = true;
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slices[s].dual_subslice[dss].eu_mask = *eu_per_dss_mask;
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}
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}
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}
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}
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/* Set devinfo masks */
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for (unsigned s = 0; s < devinfo->max_slices; s++) {
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if (!slices[s].dss_mask)
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continue;
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devinfo->slice_masks |= (1u << s);
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for (unsigned ss = 0; ss < devinfo->max_subslices_per_slice; ss++) {
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if (!slices[s].dual_subslice[ss].eu_mask)
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continue;
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devinfo->subslice_masks[s * devinfo->subslice_slice_stride +
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ss / 8] |= (1u << (ss % 8));
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for (unsigned eu = 0; eu < devinfo->max_eus_per_subslice; eu++) {
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if (!(slices[s].dual_subslice[ss].eu_mask & (1u << eu)))
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continue;
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devinfo->eu_masks[s * devinfo->eu_slice_stride +
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ss * devinfo->eu_subslice_stride +
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eu / 8] |= (1u << (eu % 8));
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}
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}
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}
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intel_device_info_topology_update_counts(devinfo);
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intel_device_info_update_pixel_pipes(devinfo, devinfo->subslice_masks);
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intel_device_info_update_l3_banks(devinfo);
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}
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static bool
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xe_query_topology(int fd, struct intel_device_info *devinfo)
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{
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struct drm_xe_query_topology_mask *topology;
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int32_t len;
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topology = xe_query_alloc_fetch(fd, DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, &len);
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if (!topology)
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return false;
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uint32_t geo_dss_num_bytes = 0, *eu_per_dss_mask = NULL;
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uint8_t *geo_dss_mask = NULL, *tmp;
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const struct drm_xe_query_topology_mask *head = topology;
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tmp = (uint8_t *)topology + len;
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const struct drm_xe_query_topology_mask *end = (struct drm_xe_query_topology_mask *)tmp;
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while (topology < end) {
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if (topology->gt_id == 0) {
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switch (topology->type) {
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case XE_TOPO_DSS_GEOMETRY:
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geo_dss_mask = topology->mask;
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geo_dss_num_bytes = topology->num_bytes;
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break;
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case XE_TOPO_EU_PER_DSS:
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eu_per_dss_mask = (uint32_t *)topology->mask;
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break;
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}
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}
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topology = (struct drm_xe_query_topology_mask *)&topology->mask[topology->num_bytes];
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}
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bool ret = true;
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if (!geo_dss_num_bytes || !geo_dss_mask || !eu_per_dss_mask) {
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ret = false;
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goto parse_failed;
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}
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xe_compute_topology(devinfo, geo_dss_mask, geo_dss_num_bytes, eu_per_dss_mask);
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parse_failed:
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free((void *)head);
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return ret;
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}
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bool
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intel_device_info_xe_get_info_from_fd(int fd, struct intel_device_info *devinfo)
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{
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@ -170,6 +305,9 @@ intel_device_info_xe_get_info_from_fd(int fd, struct intel_device_info *devinfo)
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if (xe_query_hwconfig(fd, devinfo))
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intel_device_info_update_after_hwconfig(devinfo);
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if (!xe_query_topology(fd, devinfo))
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return false;
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devinfo->has_context_isolation = true;
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devinfo->has_mmap_offset = true;
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devinfo->has_caching_uapi = false;
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