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Author SHA1 Message Date
Zan Dobersek
7fd5f76393 nir/lower_vars_to_scratch: calculate threshold-limited variable size separately 
ir3's lowering of variables to scratch memory has to treat 8-bit values as
16-bit ones when comparing such value's size against the given threshold
since those values are handled through 16-bit half-registers. But those
values can still use natural 8-bit size and alignment for storing inside
scratch memory.

nir_lower_vars_to_scratch now accepts two size-and-alignment functions,
one used for calculating the variable size and the other for calculating
the size and alignment needed for storing inside scratch memory. Non-ir3
uses of this pass can just duplicate the currently-used function. ir3
provides a separate variable-size function that special-cases 8-bit types.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29875>
 2024-08-07 14:32:28 +00:00
Marek Olšák
de83b5ef77 ac/surface/gfx12: fix setting tile_swizzle 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30503>
 2024-08-05 19:35:39 +00:00
yinjiyao
50ff1e4f86 radeonsi/vcn: add HDR sei in hevc enc 
Enable HDR sei in hevc encoder.

Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30388>
 2024-07-29 21:48:04 +00:00
David Rosca
8b1a889e45 radeonsi/vcn: Add support for QVBR rate control mode 
This rate control mode needs pre-encode enabled and currently is
supported for VCN3 and VCN4.
AV1 needs quality level scaled down from 255 to 51 range.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4024
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30221>
 2024-07-24 20:18:49 +00:00
Ruijing Dong
8a5ef9413b radeonsi/vcn: add HDR metadata obu in av1enc 
Enable HDR metadata obu in av1 encoder for
both vcn4/5.

Reviewed-by: David Rosca <david.rosca@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30237>
 2024-07-23 17:16:21 +00:00
Ruijing Dong
aa86c3a235 radeonsi/vcn: input av1 hdr metadata 
get av1 hdr metadata from frontends.

Reviewed-by: David Rosca <david.rosca@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30237>
 2024-07-23 17:16:21 +00:00
Marek Olšák
d90080b51b nir/opt_vectorize_io: optionally don't vectorize IO with different types 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11443

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29895>
 2024-07-23 16:13:17 +00:00
Marek Olšák
07ef1a8124 ac,radeonsi: set 16-bit flags in io_options optimally 
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29895>
 2024-07-23 16:13:17 +00:00
Marek Olšák
709ebd8293 amd: expose nir_io_mix_convergent_flat_with_interpolated 
The drivers need to invert how they gather flat inputs.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29895>
 2024-07-23 16:13:17 +00:00
Marek Olšák
b2d32ae246 nir: add nir_intrinsic_load_per_primitive_input, split from io_semantics flag 
Instead of having 1 bit in nir_io_semantics indicating a per-primitive
FS input, add a dedicated intrinsic for it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29895>
 2024-07-23 16:13:16 +00:00
Ganesh Belgur Ramachandra
ec4e5ef0f7 amd/common: skip lane size determination for chips without image opcodes (e.g. gfx940) 
This fixes VAAPI decode performance issues.

Fixes: 5b3e1a0532 ("radeonsi: change the compute blit to clear/blit multiple pixels per lane")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30273>
 2024-07-23 14:50:37 +00:00
Pierre-Eric Pelloux-Prayer
0c868aa94a amd: use a valid size for ac_pm4_state allocation 
If max_dw is smaller than the pm4 array the allocation size would be
smaller than sizeof(ac_pm4_state).

Fixes: 428601095c ("ac,radeonsi import PM4 state from RadeonSI")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30257>
 2024-07-22 10:09:34 +00:00
Daniel Stone
ccc6442d6f u_format: Rewrite format table to use YAML 
u_format has always had its format table in CSV. This is kind of nice
for some things, but is a serious pain to extend, especially with
optional fields.

In going through our many (many, many) duplicated tables of format
mappings, it would've been nice to add some descriptions to our central
u_format table, such as mapping to DRM FourCC, to EGLImage mappings, and
to GL internalformats for EGLImage imports. Unfortunately, doing so with
more additional fields would just make the CSV totally unreadable.

Move the CSV table to a YAML-based table and adjust the Python parsers
to suit. The resulting generated files are identical before and after
the transition.

The new parser also has a significant amount of format validation to
make it easier to catch common errors.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29649>
 2024-07-19 13:50:42 +00:00
David Rosca
8fa9e78e39 radeonsi/vcn: Support 10bit RGB for EFC input 
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30101>
 2024-07-18 13:11:13 +00:00
Samuel Pitoiset
e2882ea3e2 ac/rgp: assume GFX11_5 use the same SQTT/RGP versions as GFX11 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30225>
 2024-07-17 16:25:19 +00:00
Alex Deucher
dec4603a21 ac/surface: fix version check for gfx12 DCC 
It's 58, not 59.  The original 58 feature was not
ready so it was dropped.

Fixes: 0bb83a4060 ("ac/surface: finish display DCC for gfx12")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30212>
 2024-07-16 16:33:32 +00:00
Marek Olšák
a5b4ae67ae ac: add radeon_info::has_scratch_base_registers 
Fixes: 3b0bfd254f - radeonsi/gfx11: make flat_scratch changes for compute

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30071>
 2024-07-15 13:52:25 -04:00
Marek Olšák
0bb83a4060 ac/surface: finish display DCC for gfx12 
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30114>
 2024-07-13 02:17:37 +00:00
Marek Olšák
46071c90c7 ac/surface: finish display DCC for gfx11.5 
Fixes: 6835257246 - amd/common: update DCC for gfx11.5

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30114>
 2024-07-13 02:17:37 +00:00
Marek Olšák
11272a8d82 ac/nir: remove sleeps from gfx12 streamout code 
This is faster.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30063>
 2024-07-13 01:32:48 +00:00
Marek Olšák
1b2cd628b8 nir: rename ordered_xfb_counter_add_gfx12_amd -> ordered_add_loop_gfx12_amd 
because it can also be used by compute.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30063>
 2024-07-13 01:32:48 +00:00
Marek Olšák
1fd43bca2c radeonsi: don't use CP DMA on GFX940 
It's been defeatured.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30115>
 2024-07-13 00:58:30 +00:00
David Rosca
6cc32c609b radeonsi/vcn: Add low latency encode support 
This feature should be enabled for use cases when the lowest encoding
latency is desired, such as real-time game streaming.
Disabled by default due to increased power usage.

There is no libva interface currently that could be used for this, so
for now it can only be enabled by setting AMD_DEBUG=lowlatencyenc
environment variable.

See: https://gitlab.freedesktop.org/drm/amd/-/issues/3336

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30039>
 2024-07-11 18:33:41 +00:00
Samuel Pitoiset
cc3cb526c4 ac,radeonsi: add ac_is_reduction_mode_supported() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30074>
 2024-07-10 07:57:42 +00:00
Pierre-Eric Pelloux-Prayer
e7b200f20b ac/info: remove has_syncobj 
syncobj support is now required so these features are always available.
This is the same as 02fe3c32cd, without the radeonsi parts
to not break radeonsi on radeon.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29876>
 2024-07-09 15:07:27 +02:00
Pierre-Eric Pelloux-Prayer
2021813450 Revert "ac, radeonsi: remove has_syncobj, has_fence_to_handle" 
This reverts commit 02fe3c32cd.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11352
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29876>
 2024-07-09 15:07:27 +02:00
Tim Huang
e322b2b683 amd: add GFX v11.5.2 support 
This is to enable GFX v11.5.2 support.

Signed-off-by: Tim Huang <Tim.Huang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29930>
 2024-07-02 12:05:23 +00:00
David Heidelberg
68215332a8 build: pass licensing information in SPDX form 
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29972>
 2024-06-29 12:42:49 -07:00
Georg Lehmann
080e03d021 ac/nir: enable ford, funord, fneo, fequ, fltu, fgeu 
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29467>
 2024-06-27 08:12:30 +00:00
Pierre-Eric Pelloux-Prayer
6ec95b990e ac/nir: don't use the compute blit for PIPE_FORMAT_R5G6B5_UNORM 
It breaks spec@arb_pixel_buffer_object@texsubimage array pbo and
spec@arb_pixel_buffer_object@texsubimage pbo with some formats:

72,3,0: test = 140,0,8,255 ref = 148,0,8,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_R3_G3_B2
  region: 5, 3  116 x 11
72,3,0: test = 140,0,8,255 ref = 148,0,8,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_RGB5
  region: 33, 3  78 x 11
72,10,0: test = 140,0,41,255 ref = 148,0,41,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_1D_ARRAY
  internal format: GL_RGB5_A1
  region: 3, 10  124 x 33
72,19,4: test = 140,65,74,255 ref = 148,65,74,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_R3_G3_B2
  region: 36, 19  81 x 18
12,36,4: test = 25,66,140,255 ref = 25,66,148,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_RGB5
  region: 12, 9  30 x 39
72,22,2: test = 140,33,90,255 ref = 148,33,90,255 (comparing 8 bits)
texsubimage failed
  target: GL_TEXTURE_2D_ARRAY
  internal format: GL_RGB5_A1
  region: 39, 22  36 x 37

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Pierre-Eric Pelloux-Prayer
abd048124a ac/surface: reject modifiers with retile_dcc and bpe != 32 
radv has a comment in radv_meta_dcc_retile.c:
   * BPE is always 4 at the moment and the rest is derived from the tilemode.
radeonsi has in si_retile_dcc:
   /* We have only 1 variant per bpp for now, so expect 32 bpp. */
   assert(tex->surface.bpe == 4);

This fixes ext_image_dma_buf_import-modifiers for radeonsi.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29612>
 2024-06-26 14:02:13 +00:00
Marek Olšák
932e8c7768 ac/nir/cdna: don't use image_descriptor intrinsics if the src is a descriptor 
Fixes: 30af861bff - radeonsi: restructure (rewrite) the compute blit shader

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29852>
 2024-06-25 10:09:08 +00:00
Marek Olšák
8023e89d11 ac/nir/cdna: ignore image_descriptor intrinsics 
Fixes: 30af861bff - radeonsi: restructure (rewrite) the compute blit shader

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29852>
 2024-06-25 10:09:08 +00:00
Marek Olšák
fec0a9fcdf ac/nir/cdna: allow 16-bit coordinates 
This can occur with the new compute blit shader.

Fixes: 30af861bff - radeonsi: restructure (rewrite) the compute blit shader

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29852>
 2024-06-25 10:09:07 +00:00
Samuel Pitoiset
ee2400acf1 ac/parse_ib: dump PKT3_DISPATCH_{TASKMESH_GFX,TASKMESH_DIRECT_ACE} 
Useful for inspecting command buffers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29821>
 2024-06-25 09:20:48 +00:00
Alyssa Rosenzweig
da752ed7c1 treewide: use nir_def_replace sometimes 
Two Coccinelle patches here. Didn't catch nearly as much as I would've liked but
it's a start.

Coccinelle patch:

    @@
    expression intr, repl;
    @@

    -nir_def_rewrite_uses(&intr->def, repl);
    -nir_instr_remove(&intr->instr);
    +nir_def_replace(&intr->def, repl);

Coccinelle patch:

    @@
    identifier intr;
    expression instr, repl;
    @@

    nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    ...
    -nir_def_rewrite_uses(&intr->def, repl);
    -nir_instr_remove(instr);
    +nir_def_replace(&intr->def, repl);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com> [broadcom]
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com> [lima]
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> [etna]
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com> [r300]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29817>
 2024-06-21 15:36:56 +00:00
Pierre-Eric Pelloux-Prayer
14974fd097 ac/llvm: implement WA in nir to llvm 
LLVM implements multiple workarounds for gfx11.
The problem is that they're not applied for shaders built in
parts.

LLVM will be modified to be more conservative and apply the
workaround in more places but in the meantime, add a simpler
implementation in the NIR to LLVM backend: insert a wait at
the end of each shader part.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10785
Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29304>
 2024-06-20 13:14:33 +00:00
Dave Airlie
6a464401d5 ac/radv/radeon: move film grain init to common code. 
Share the film grain code between users.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29747>
 2024-06-19 20:51:53 +00:00
Dave Airlie
57535969cb ac/radv/radeonsi: move av1 ctx/probs size/filling to common code. 
All the av1 prob and ctx sizing code can be shared between
radv and radeonsi here.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29747>
 2024-06-19 20:51:52 +00:00
Timur Kristóf
0355364743 ac/nir/tess: Fix per-patch output VRAM mapping. 
VARYING_SLOT_PATCH0 is greater than 64 so it is wrong to use it
with BITFIELD64_BIT. Check for VARYING_SLOT_TESS_LEVEL_* properly
when mapping output locations in VRAM.

Fixes: 2cf7f282df
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11253
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29696>
 2024-06-18 12:06:21 +00:00
Timur Kristóf
0f0ebd8512 ac/nir/tess: Fix per-patch output LDS mapping. 
VARYING_SLOT_PATCH0 is greater than 64 so it is wrong to use it
with BITFIELD64_BIT. Check for VARYING_SLOT_TESS_LEVEL_* properly
when mapping output locations in LDS.

Fixes: c61eb54806
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29696>
 2024-06-18 12:06:21 +00:00
Timur Kristóf
348b8859dc ac/nir/tess: Only write tess factors that the TES reads. 
Otherwise we would write to a memory location reserved
for another per-patch output.

Fixes: 2cf7f282df
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11324
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29696>
 2024-06-18 12:06:21 +00:00
Alyssa Rosenzweig
15257b65c6 treewide: use nir_metadata_control_flow 
Via Coccinelle patch:

    @@
    @@

    -nir_metadata_block_index | nir_metadata_dominance
    +nir_metadata_control_flow

...plus some manual fixups for call sites missed by coccinelle.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
Acked-by: Juan A. Suarez Romero <jasuarez@igalia.com> [broadcom]
Acked-by: Vasily Khoruzhick <anarsoul@gmail.com> [lima]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29745>
 2024-06-17 16:28:14 -04:00
Daniel Schürmann
f3d8bd18dd nir: introduce discard_is_demote compiler option 
This new option indicates that the driver emits the same
code for nir_intrinsic_discard and nir_intrinsic_demote.
Otherwise, it is assumed that discard is implemented as
terminate.

spirv_to_nir uses this option in order to directly emit
nir_demote in case of OpKill.

RADV GFX11:
Totals from 3965 (4.99% of 79439) affected shaders:
MaxWaves: 119418 -> 119424 (+0.01%); split: +0.03%, -0.03%
Instrs: 1608753 -> 1620830 (+0.75%); split: -0.18%, +0.93%
CodeSize: 8759152 -> 8785152 (+0.30%); split: -0.18%, +0.48%
VGPRs: 152292 -> 149232 (-2.01%); split: -2.37%, +0.36%
Latency: 9162314 -> 10033923 (+9.51%); split: -0.46%, +9.97%
InvThroughput: 1491656 -> 1493408 (+0.12%); split: -0.10%, +0.22%
VClause: 21424 -> 21452 (+0.13%); split: -0.31%, +0.44%
SClause: 53598 -> 55871 (+4.24%); split: -2.15%, +6.39%
Copies: 90553 -> 90462 (-0.10%); split: -2.91%, +2.81%
Branches: 16283 -> 16311 (+0.17%)
PreSGPRs: 113993 -> 113254 (-0.65%); split: -1.84%, +1.19%
PreVGPRs: 110951 -> 108914 (-1.84%); split: -2.08%, +0.24%
VALU: 963192 -> 963167 (-0.00%); split: -0.01%, +0.01%
SALU: 87926 -> 90795 (+3.26%); split: -2.92%, +6.18%
VMEM: 25937 -> 25936 (-0.00%)
SMEM: 110012 -> 109799 (-0.19%); split: -0.20%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>
 2024-06-17 19:37:15 +00:00
Daniel Schürmann
d5821bdf7d radv: emit discard as demote by default 
Also removes radv_lower_discard_to_demote debug option.

Totals from 1506 (1.90% of 79439) affected shaders: (GFX11)
MaxWaves: 46432 -> 46448 (+0.03%)
Instrs: 664515 -> 667914 (+0.51%); split: -0.15%, +0.67%
CodeSize: 3569656 -> 3583440 (+0.39%); split: -0.12%, +0.51%
VGPRs: 50100 -> 49680 (-0.84%); split: -0.96%, +0.12%
Latency: 4221359 -> 4217875 (-0.08%); split: -0.67%, +0.59%
InvThroughput: 628809 -> 625565 (-0.52%); split: -0.53%, +0.02%
VClause: 9948 -> 9965 (+0.17%); split: -0.36%, +0.53%
SClause: 19656 -> 19695 (+0.20%); split: -0.77%, +0.97%
Copies: 32113 -> 33513 (+4.36%); split: -1.59%, +5.95%
Branches: 8406 -> 8378 (-0.33%)
PreSGPRs: 42328 -> 42555 (+0.54%); split: -0.39%, +0.93%
PreVGPRs: 38451 -> 38203 (-0.64%); split: -0.78%, +0.14%
VALU: 390770 -> 390208 (-0.14%); split: -0.16%, +0.02%
SALU: 43318 -> 46374 (+7.05%); split: -0.08%, +7.14%
VMEM: 15052 -> 15051 (-0.01%)
SMEM: 37225 -> 37215 (-0.03%); split: -0.03%, +0.01%

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27617>
 2024-06-17 19:37:15 +00:00
Samuel Pitoiset
0e62c728eb ac/surface: add NBC view support on GFX12 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29676>
 2024-06-17 14:46:36 +00:00
Pierre-Eric Pelloux-Prayer
5c50e028d1 ac/sqtt: make VA helpers static 
They're only used from ac_sqtt so don't expose them.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25397>
 2024-06-14 10:32:17 +02:00
Leo Liu
448c716358 ac/surface/tests: add the test for ADDR3_256B_2D 
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29541>
 2024-06-11 12:29:11 -04:00
Leo Liu
59e813d953 ac/surface: add GFX12 256B tile mode for video 
With VCN5, the DPB buffer uses gfx12 tile/swizzle mode.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29541>
 2024-06-11 12:29:11 -04:00
Samuel Pitoiset
a373ba92c3 amd: add a common implementation for SQTT using PM4 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29499>
 2024-06-11 06:46:55 +00:00