ac,radeonsi: add ac_is_reduction_mode_supported()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30074>
This commit is contained in:
Samuel Pitoiset 2024-07-08 17:50:01 +02:00 committed by Marge Bot
parent 2d29b8b01e
commit cc3cb526c4
3 changed files with 39 additions and 28 deletions

View file

@ -766,3 +766,37 @@ ac_alpha_is_on_msb(const struct radeon_info *info, enum pipe_format format)
return comp_swap != V_028C70_SWAP_STD_REV && comp_swap != V_028C70_SWAP_ALT_REV;
}
/* GFX6-8:
* - no integer format support
* - no depth format support (depth formats without shadow samplers are supported,
* but that's not enough)
* - only single-channel formats are supported
* - limitations of early chips (GFX6 only): no R9G9B9E5 support
*
* GFX9+:
* - all formats are supported
*/
bool
ac_is_reduction_mode_supported(const struct radeon_info *info, enum pipe_format format,
bool shadow_samplers)
{
const struct util_format_description *desc = util_format_description(format);
if (info->gfx_level <= GFX8) {
/* old HW limitations */
if (info->gfx_level == GFX6 && format == PIPE_FORMAT_R9G9B9E5_FLOAT)
return false;
/* reject if more than one channel */
if (desc->nr_channels > 1)
return false;
/* no integer or depth format support */
if (util_format_is_pure_integer(format) ||
(shadow_samplers && util_format_has_depth(desc)))
return false;
}
return true;
}

View file

@ -66,6 +66,10 @@ ac_simplify_cb_format(enum pipe_format format);
bool
ac_alpha_is_on_msb(const struct radeon_info *info, enum pipe_format format);
bool
ac_is_reduction_mode_supported(const struct radeon_info *info, enum pipe_format format,
bool shadow_samplers);
#ifdef __cplusplus
}
#endif

View file

@ -2245,38 +2245,11 @@ static bool si_is_zs_format_supported(enum pipe_format format)
return ac_is_zs_format_supported(format);
}
/* GFX6-8:
* - no integer format support
* - no depth format support (depth formats without shadow samplers are supported,
* but that's not enough)
* - only single-channel formats are supported
* - limitations of early chips (GFX6 only): no R9G9B9E5 support
*
* GFX9+:
* - all formats are supported
*/
static bool si_is_reduction_mode_supported(struct pipe_screen *screen, enum pipe_format format)
{
struct si_screen *sscreen = (struct si_screen *)screen;
const struct util_format_description *desc = util_format_description(format);
if (sscreen->info.gfx_level <= GFX8) {
/* old HW limitations */
if (sscreen->info.gfx_level == GFX6 &&
format == PIPE_FORMAT_R9G9B9E5_FLOAT)
return false;
/* reject if more than one channel */
if (desc->nr_channels > 1)
return false;
/* no integer or depth format support */
if (util_format_is_pure_integer(format) ||
util_format_has_depth(desc))
return false;
}
return true;
return ac_is_reduction_mode_supported(&sscreen->info, format, true);
}
static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,