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amd/common: skip lane size determination for chips without image opcodes (e.g. gfx940)

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This fixes VAAPI decode performance issues.

Fixes: 5b3e1a0532 ("radeonsi: change the compute blit to clear/blit multiple pixels per lane")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30273>
This commit is contained in:
Ganesh Belgur Ramachandra 2024-07-20 00:26:36 +05:30 • committed by Marge Bot
parent 0cb3ace969
commit ec4e5ef0f7
1 changed files with 2 additions and 1 deletions
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3
src/amd/common/ac_nir_meta_cs_blit.c
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@ -679,7 +679,8 @@ ac_prepare_compute_blit(const struct ac_cs_blit_options *options,
*/
if (blit->dst.surf->bpe <= 8 && (is_resolve ? src_samples : dst_samples) <= 4 &&
/* Small blits don't benefit. */
width * height * depth * blit->dst.surf->bpe * dst_samples > 128 * 1024) {
width * height * depth * blit->dst.surf->bpe * dst_samples > 128 * 1024 &&
info->has_image_opcodes) {
if (is_3d_tiling) {
/* Thick tiling. */
if (!is_clear && blit->src.surf->is_linear) {