This is only needed for original 965G/GM clipper code, which only exists
in the legacy compiler. Send it off to live with the elk.
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>
This is used in exactly one place in crocus, which already has a comment
indicating that this code is needed for original Gfx4 hardware. Just
replace that with a verx10 == 40 check.
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>
This is used by a single place in ISL only for sanity checking the
decisions it has already made. The knowledge is already all centralized
in ISL these days, so we don't need a device info bit.
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>
This code is a lot of mess for no real benefit. It's existed since
the dawn of isl, and serves to let you optimize out a single check
in release builds for Ironlake and Sandybridge systems. All other
uses are for asserts, which already get compiled out in release mode.
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>
This code, since the dawn of time, has had a redundant check for gen5-6
separate stencil in the final else clause:
} else if (doing separate stencil on gen5-6) {
return compact
} else {
if (doing separate stencil on gen5-6)
return compact
...
}
We can eliminate that one. The else clause then has a single if, so it
can be folded into the "else if" ladder alongside the others.
Reviewed-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33764>
If an image gets created with unsupported parameters (which is a pretty
complex thing to check), it's probably better to just return an error
rather than panic, especially since Rust panics happen even in release
builds.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33990>
They're so different that sharing the code really wasn't buying us
anything. It's way easier to read if the two are separated.
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33990>
Compositors sometime try to import BOs with lower alignments than 128B.
This seems particularly common in the case of cursor images but it can
also happen on other BOs allocated by the old nouveau GL driver. As
long as we avoid rendering to them (which NVK will do), the
texture/image hardware is fine as long as they're at least 32B-aligned.
Panicing in this case isn't very nice to compositors.
Backport-to: 25.0
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33990>
We can do this by just enabling the fall-back path whenever we detect
something that's not nicely aligned.
Backport-to: 25.0
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33990>
When importing libdrm_radeon code [1][2] it was somehow missed
that what libdrm has in one r600_pci_ids.h, Mesa has split
into r600_pci_ids.h and radeonsi_pci_ids.h. So, devices
with ids from radeonsi_pci_ids.h were not considered valid for
radeon_surface_manager_new.
This commit changes that, thus fixing radeonsi for these
devices.
[1] commit 1299f5c50a
[2] commit 3aa7497cc0
Fixes: 1299f5c50a
Signed-off-by: Ivan A. Melnikov <iv@altlinux.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33940>
for indirect GS, do it in the indirect kernel (not the pre-GS)
for direct, do it on the host (not the pre-GS)
we don't want pre-GS.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33901>
to make it easier for people (especially newcomers to the project) to add review
tags, we need a database mapping gitlab usernames to author names & emails. that
way, if someone just comments "rb" or whatever, there's a direct way to look
that up. this comimt adds a list of current contributors with the following
methodology:
1. first, I grabbed all names + emails of recent authors, with mailmap applied,
as proxy for active contributors:
$ git log --since=2025-01-01 --pretty='%aN,%aE,'|sort | uniq
2. then, I scraped usernames via the gitlab api attempting to match by name. I
don't want to hammer the gitlab api too much which is why I tried to keep the
list in #1 as small as possible.
import gitlab
import subprocess
import tempfile
import sys
import urllib.request
import csv
gl = gitlab.Gitlab('https://gitlab.freedesktop.org', private_token=...)
names = {}
with open('dump.csv') as csvfile:
spamreader = csv.reader(csvfile)
for row in spamreader:
if len(row) == 3:
names[row[0]] = row[1]
for name in names:
users = gl.users.list(search=name)
print(', '.join([name, names[name]] + [u.username for u in users]))
3. finally, I fixed up various data issues by hand. there were cases of both
people with multiple usernames (I tried to pick the one that's actually in
use), and people whose name on their profile does not match the name in their
commits (I tried to determine the username from searching gitlab manually,
but dropped a number of such authors when it was nontrivial to figure out. I
am a regular reviewer across the tree so if I don't recognize your name
you're probably not that active, sorry.)
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33896>
..or "the one where Alyssa gets jealous by b4".
Those of us who have stuck around a while have a habit of just commenting "rb"
or "ab" on MRs. which raises the question for everyone else of what name/email
to use. I've personally built up a collection of 36 (!!) different
shell aliases to apply different people's trailers. I think other people do
similarly.
This calls for better tooling. This patch adds a little script for applying
review trailers given a fuzzy match on the reviewer's name. I recommend
contributors alias it to something like `mrb`, then you can do things like:
mrb alyssa
mrb -a faith
to add a review tag for me or an acked-by tag for Faith.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33896>
It is expected that inputs and prefetches are always in the first block.
However, ir3_create_empty_preamble would create blocks before the first
one, leaving inputs after the preamble. This causes issues with
(probably among others) spilling/RA where precolored inputs could
illegally reuse the spill base register.
Fixes RA validation failures on a7xx for
dEQP-VK.ray_query.multiple_ray_queries.vertex_shader
Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: f3026b3d3e ("ir3: add some preamble helpers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33977>
For empty BVHs we shouldn't emit any leaf nodes, but there is one
invocation to encode the root node. Guard leaf node encoding so that
invocation doesn't try writing any leaves.
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33985>
Prime blit can be used in setups like venus on lavapipe over vtest. It's
native env so Venus relies on renderer side driver to tell about the pci
info, while lavapipe doesn't implement that extension, which ends up
with mismatched gpu thus prime blit.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33956>
The swizzle check was too strict, we actually don't care about the
swizzle on the constant source at this point, it is only checked
later whether the constant source actually has the correct form.
So this effectively enables INV and BIAS presub on R300/R400.
RV370 stats:
total instructions in shared programs: 85379 -> 84948 (-0.50%)
instructions in affected programs: 15669 -> 15238 (-2.75%)
helped: 336
HURT: 81
total presub in shared programs: 1318 -> 2991 (126.93%)
presub in affected programs: 797 -> 2470 (209.91%)
helped: 0
HURT: 514
total omod in shared programs: 387 -> 384 (-0.78%)
omod in affected programs: 9 -> 6 (-33.33%)
helped: 3
HURT: 0
total temps in shared programs: 13290 -> 13243 (-0.35%)
temps in affected programs: 1388 -> 1341 (-3.39%)
helped: 91
HURT: 52
total consts in shared programs: 81922 -> 81855 (-0.08%)
consts in affected programs: 173 -> 106 (-38.73%)
helped: 67
HURT: 0
total cycles in shared programs: 126746 -> 126560 (-0.15%)
cycles in affected programs: 30752 -> 30566 (-0.60%)
helped: 255
HURT: 124
LOST: shaders/godot3.4/22-69.shader_test FS
GAINED: shaders/ck2/172.shader_test FS
GAINED: shaders/tesseract/389.shader_test FS
GAINED: shaders/tesseract/393.shader_test FS
GAINED: shaders/unity/64-DeferredPointShadows.shader_test FS
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33915>
Previously asynchronous descriptor set allocation is only enabled when
the VK_DESCRIPTOR_POOL_CREATE_FREE_DESCRIPTOR_SET_BIT bit is not set.
However, some engine would use that bit but alloc/free with identical
descriptor set layout. So this change extends the async set alloc to
cover that since the spec has guaranteed no fragmentation there.
Besides, a pool before any descriptor set free is also considered w/o
fragmentation. so this change extends to cover here as well. Both
would also help with dEQP run time since all descriptor pools involved
are with that bit set.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33966>
We get a kernel message "You are adding an unorder point to timeline!"
on many CTS runs. This stems from us SIGNALing the queue syncobj then
WAITing but not reseting it. It is assumed by the time we get to
panvk_queue_submit_init_signals() that the value is 0, however it is 1
due to the previous calls.
Signed-off-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Fixes: 5544d39f ("panvk: Add a CSF backend for panvk_queue/cmd_buffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33943>
VEGA10, RENOIR, NAVI10, RAPHAEL and NAVI31 are covered, they passed
100% of 25 runs each.
NAVI21 and VANGOGH still don't enable video testing in CI because I
got few hangs during my last stress test. Need to be stress tested
again.
Note that the kernel in Mesa CI is too old and doesn't have latest
firmwares that should fix the remaining failures.
GFX6-8 have different issues like GPU hangs on Polaris10, so it's not
yet enabled in CI.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33968>
This is not needed now when deinterlace can handle non-interlaced
buffers. Also this forces the buffer as interlaced which doesn't work
on radeonsi anymore.
This reverts commit 0ee4506c3a.
Cc: mesa-stable
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33927>
