Commit graph

200846 commits

Author SHA1 Message Date
Valentine Burley
7d66facfda ci: Skip broken PenumbraOverture trace for zink and freedreno
This trace contains generated GL IDs from the time it was recorded,
making it invalid.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Reviewed-by: Mike Blumenkrantz <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33256>
2025-01-29 04:16:25 +00:00
Daniel Stone
101065642d ci/debian: Upgrade Debian images to LLVM 19
LLVM 15 is pretty old, and notably not supported by either ANGLE nor
Skia anymore. So let's move up to LLVM 19 using packages provided by
LLVM themselves, apart from PPC and ARMv7 which don't have builds.

The Skia build now requires a bunch of new warning exclusions; hopefully
most of these are no longer needed when we can upgrade Skia shortly.

The ci-deb-repo revision has also been bumped to get us a new version of
xtensor which builds with LLVM 19, and a version of spirv-tools which
also works with LLVM 19.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Closes: mesa/mesa#11538
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Daniel Stone
55e9fe9d37 ci: Require LLVM_VERSION to be set explicitly
Stop falling back to 15 in random places; make sure it's set clearly
every time we want to use it.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Daniel Stone
bb01f3ae6c ci: Define LLVM_VERSION as a container property
The version of LLVM in use is defined by the version of LLVM that's been
installed, which is a property of the container. Shift to declaring it
within the container variables, not in random leaf build jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Daniel Stone
f5618315f1 ci/fedora: Install which into build image
We use this for a bunch of stuff, so make sure it's installed. Also make
sure the package list remains strictly in alphabetical order.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Daniel Stone
d5797f6ae4 ci: Move build containers above test containers
Nothing big, but it is needed to resolve YAML anchors later.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Daniel Stone
f96abf7f1a ci: Remove obsolete compiler-wrapper
We don't actually need this anymore. We were previously using it to find
ccache, but Meson will do this for us. Now that we pass
-Wl,--fatal-warnings, we don't need to pass -Werror to the link stage
either.

This removes two shell execs, one subshell, and one call to each of grep
and printf, per compile.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:28 +00:00
Eric Engestrom
439408229b ci: make linker warnings fatal
... excluding the warning for emitting a LOAD segment with RWX
permissions for libglapi, an issue which has persisted for some time.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
Daniel Stone
4c3d2af001 ci: Disable Werror on wrapped subprojects
Enabling Werror on our code is good, but it's less good on external
projects. Some of the Rust subprojects are now failing due to warnings
exposed by the newer Rust toolchain in Fedora, which we don't care about.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
Daniel Stone
87809f6236 pipe_loader: Fix pipe_i915 with the dynamic loader
When building for the dynamic loader used by e.g. Clover, pipe_i915 was
the only target failing to declare a driver descriptor. This becomes an
error with more aggressive linkers.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Fixes: 87392385b5 ("gallium/drm: Define the DRM entrypoints in drm_helper.h")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
Daniel Stone
52f6503d57 ci: Let rootfs builds run for 2 hours (!)
We now have to do five builds of dEQP: one each for tools, GL, GLES,
Vulkan (release branch), and Vulkan (main).

dEQP is not a quick build, with even the tools build taking ten minutes,
at least three of which go to just pulling the SPIRV-Tools source.

Building all five takes a cumulative 60 minutes (10 tools, 11 GL, 9
GLES, 15 VK release, 13 VK main). That doesn't give us a load of time to
build everything else we need.

Two hours is obviously a completely unreasonable amount of time to spend
doing builds, especially for jobs which shouldn't really exist. But the
yak shave to allow the container jobs to be able to run on non-b2c
hardware has been a long one, and with no big-bang solution turning up
any time soon, we need to be able to actually do rootfs builds.

So, let's do the worst possible thing and go for a gigantic timeout.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
Daniel Stone
1736ea4ca8 ci: Give much more time to ASan and UBSan jobs
Sitting here trying to get something else done tonight, I watched the
ASan and UBSan jobs, both on AArch64 and x86_64, regularly blow through
their timeouts.

They should be fixed to do less, but this makes them at least succeed in
the meantime.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
Daniel Stone
51c530a2c3 ci: Slash ASan and UBSan build coverage
Building and linking drivers, Rust code, and tools, takes an inordinate
amount of time with sanitisers. That could be justified if we used the
results to test, but we don't.

Reduce the coverage to get reasonable runtimes back.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
Daniel Stone
be00764d05 ci: Don't run Meson tests in critical-path jobs
Running the Meson tests doesn't take forever, but it does take a
noticeable amount of time.

For jobs in the critical path - like debian-testing and debian-arm64 -
we need them to complete as soon as possible to produce a build for the
hardware tests to consume. Running the tests here lengthens that time,
and introduces more hazard since the tests have previously been prone to
hitting timeouts, requiring the whole job to be retried before we can
proceed. These jobs also have build-only jobs which are not in the
critical path, and can run the tests just as well.

Running the tests under sanitisers is just too slow to deal with in
pre-merge pipelines.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33137>
2025-01-29 03:23:27 +00:00
David Tobolik
49b20a88db rusticl/style: add util for conversion with err
NEW util/conversion.rs

Adds traits `TryFromWithErr` and `TryIntoWithErr` and their
implementation for types with `TryFrom` and `TryInto` traits

former
```
try_into().map_err(|_| CL_OUT_OF_HOST_MEMORY)
try_from(val).map_err(|_| CL_OUT_OF_HOST_MEMORY)
```
can now be written as
```
try_into_with_err(CL_OUT_OF_HOST_MEMORY)
try_from_with_err(val, CL_OUT_OF_HOST_MEMORY)
```

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33267>
2025-01-29 02:51:21 +00:00
David Tobolik
98f0f6594a rusticl/style: use Arc::clone instead of .clone()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33267>
2025-01-29 02:51:21 +00:00
Job Noorman
f577118fe1 ir3/a7xx: enable delayed src2 read for all cat3 instructions
cat3 instructions read their 3rd src later than their first two srcs.
Pre-a7xx, this was only supported for mad(sh) but on a7xx, it works for
all cat3 instructions.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
992a6cc050 ir3/a7xx: update delays slots
The delay slots on a7xx are:
- ALU to ALU: 2
- Non-ALU: 5
- cat3 src2 read: 1

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
5460be5d33 ir3: make delay slots a compiler property
They changed on a7xx so we want to make it configurable.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
2c7c62dfd9 ir3: add helper to calculate src read delay
cat3 instructions read their 3rd src later than their first two srcs.
This was implemented in two different places: once for scheduling and
once for legalization. Extract this logic in a new helper and also add
similar logic for gat/swz there (which the scheduling logic failed to
account for).

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33183>
2025-01-29 02:19:50 +00:00
Job Noorman
e7ac1094f6 ir3: rematerialize preamble defs in block dominated by sources
Preamble defs were rematerialized at the end of the preamble. However,
when some of the sources were defined inside control flow, this would
lead to these sources not dominating their use. Fix this by finding the
block that is dominated by all sources and inserting the new instruction
there.

Also make sure we only de-duplicate instructions if the new instruction
is dominated by the existing one.

Fixes a NIR validation error in Devil may cry 5.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: fdfe86aa52 ("ir3: Expand preamble rematerialization")
Fixes: 6a744ddebc ("ir3: Initial support for pushing globals with ldg.k")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33270>
2025-01-29 01:45:59 +00:00
Connor Abbott
5f3cad0026 tu: Add missing assignment to shared_viewport
This was accidentally deleted when rewriting to use common Vulkan
dynamic state. This meant we wouldn't correctly fall back when someone
accidentally used FDM together with multiple viewports.

Fixes: 97da0a7734 ("tu: Rewrite to use common Vulkan dynamic state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33241>
2025-01-29 01:17:48 +00:00
Job Noorman
1adf2c9d7c ir3: schedule alias.rt at the end of the preamble
Scheduling an alias.rt right before an alias.tex causes a GPU hang.
Follow the blob and schedule all alias.rt at the end of the preamble to
prevent this from happening.

Fixes a hang in Borderlands 3 on medium or higher graphics settings.

Signed-off-by: Job Noorman <jnoorman@igalia.com>
Fixes: 0aa9678d4d ("ir3: add support for alias.rt")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33238>
2025-01-29 00:46:22 +00:00
Alyssa Rosenzweig
3bfcc4f323 clc,libagx: automatically set lang version
bit less meson cargocult.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
2025-01-28 23:01:32 +00:00
Alyssa Rosenzweig
9f460eadab clc,libagx: drop --in for mesa_clc
just accept the arguments as-is. this matches how gcc/clang actually work
and simplifies the meson.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
2025-01-28 23:01:32 +00:00
Alyssa Rosenzweig
164a161279 meson: project-wide fs = import('fs')
reduces a bit of boilerplate.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33242>
2025-01-28 23:01:32 +00:00
Corentin Noël
61626296f2 virgl/ci: Re-enable virgl-traces
This reverts commit 3a7737ffb5

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33265>
2025-01-28 21:07:09 +00:00
Samuel Pitoiset
18c7eafcdc radv: fix programming mip level for TILED_SUB_WINDOWS on GFX12
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33252>
2025-01-28 20:32:11 +00:00
Samuel Pitoiset
7c949f1760 radv: fix programming pitches for LINEAR_SUB_WINDOW on GFX12
GFX12 supports up to 64k images.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33252>
2025-01-28 20:32:11 +00:00
Ruijing Dong
1a942f53cc radeonsi/vcn: center mv map buffer changed in vcn5.x
center mv map buffer size changed on vcn5.x, please be aware
that vcn5.0 will not enable 2pass untill vcn5.x.

Reviewed-by: David Rosca <david.rosca@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33215>
2025-01-28 19:50:16 +00:00
Lucas De Marchi
1bd6a2efe1 intel/tools: Fix Xe KMD error dump parser
Xe KMD originally put the exec queue snapshot in the wrong topic,
XE_TOPIC_GUC_CT. Add it to the right one while still keeping a fallback
to the previous place so the new version of the tool is able to parse
both before and after the kernel change.

Based on previous version by José Roberto de Souza <jose.souza@intel.com>
at https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32617

Cc: stable
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33177>
2025-01-28 19:11:26 +00:00
Pavel Ondračka
220590f41a r300: fix memory leak in contant remaping
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
f00f08c02d r300: remove support for register arrays from nir_to_rc
Backend can't handle it and no app which we can reasonably run uses
this anyway AFAIK.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
89c06ea0f6 r300: get rid of some texture fixups
Textures opcodes can't read from the contant registers, however we can
just handle this fine in the native swizzle pass. Others like saturate
for tex instructions) can't happen anyway since we swithed to nir_to_tgsi
long time ago. However, keep the asserts just to be safe.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
47207dcb0b r300: get rid of the register rename pass
The pass tried to convert shaders to a SSA-like form. However since
we no longer allocate registers in NIR, and we try hard to keep the
SSA-like form during the later passes, this is now superfluous.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
c45f02461c r300: don't allocate fs registers when translating from NIR
So we can get the ssa-like form right away and we don't have to generate
it again with the register rename pass later.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
0e9b90dcf4 r300: use ssa-like form for backend texture lowering
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
ca70270a5e r300: add some more nir cleanup compiler passes
We need this to prevent some regressions in the later commits.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
e832bc1ae5 r300: use ssa-like form for gl_FragCoord transformation
Lots of backend code will be simpler if we have ssa-like (as much as we
can have with vec4), so just don't reuse registers here.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
14fe3e9886 r300: delete backend shadow lowering code
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
d1c7244b6f r300: reswizzle some shadow texture calculations to use w channel
Prevents shader-db regression, since NIR puts just everything to x and the
pair scheduling is not smart enough to fix it later, espetially after
presubtract happens.

Together with the previous patches that move the shadow lovering to NIR
this results in the following shader-db stats:

RV530:
total instructions in shared programs: 129598 -> 128697 (-0.70%)
instructions in affected programs: 19001 -> 18100 (-4.74%)
helped: 124
HURT: 9
total presub in shared programs: 8554 -> 8314 (-2.81%)
presub in affected programs: 1099 -> 859 (-21.84%)
helped: 17
HURT: 50
total temps in shared programs: 17514 -> 17000 (-2.93%)
temps in affected programs: 1368 -> 854 (-37.57%)
helped: 45
HURT: 18
total cycles in shared programs: 191286 -> 190593 (-0.36%)
cycles in affected programs: 32369 -> 31676 (-2.14%)
helped: 110
HURT: 29

RV410:
total instructions in shared programs: 112805 -> 112618 (-0.17%)
instructions in affected programs: 7089 -> 6902 (-2.64%)
helped: 65
HURT: 21
total presub in shared programs: 3244 -> 3314 (2.16%)
presub in affected programs: 228 -> 298 (30.70%)
helped: 7
HURT: 47
total temps in shared programs: 18163 -> 18138 (-0.14%)
temps in affected programs: 710 -> 685 (-3.52%)
helped: 36
HURT: 19
total cycles in shared programs: 169530 -> 169369 (-0.09%)
cycles in affected programs: 11304 -> 11143 (-1.42%)
helped: 63
HURT: 27

The stats are a bit less awesome for Rv410, since it can't run the heavy
Unigine Tropics shaders where this helps the most due to the TEX
indirection limits.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
296da387c0 r300: move shadow lowering to NIR
This means we now do fragment shader-variants at the NIR level and we
therefore need to run nir_to_rc translation later during the shader
variant creation.

This is a temporary instruction count as well as registers count
regression, due to NIR putting everything to x instead of w, this is
fixed in the next commit which also shows some nice shader-db stats
improvements in total.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Pavel Ondračka
ea41ecd130 r300: fix presubtract assert
We only care that the negates of the relevant components are the same.
Specifically the assert would incorectly trigger for code like this
ADD temp[3].x, 1.250000 (0x3a).-x___, -const[0].x___;

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <None>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
2025-01-28 17:42:53 +00:00
Georg Lehmann
b23ff87db4 aco/sched_ilp: base latency and issue cycles on aco_statistics
This matters for trans and scalar fpu instructions.

Foz-DB GFX1150:
Totals from 53894 (67.90% of 79377) affected shaders:
Instrs: 38528421 -> 38481337 (-0.12%); split: -0.16%, +0.04%
CodeSize: 200206016 -> 200023916 (-0.09%); split: -0.12%, +0.03%
Latency: 265011734 -> 264303762 (-0.27%); split: -0.28%, +0.02%
InvThroughput: 53804490 -> 53696097 (-0.20%); split: -0.21%, +0.01%
VClause: 736996 -> 736988 (-0.00%); split: -0.00%, +0.00%
SClause: 1118494 -> 1118474 (-0.00%); split: -0.01%, +0.01%
VALU: 21982349 -> 21982358 (+0.00%); split: -0.00%, +0.00%

Foz-DB Navi31:
Totals from 50791 (63.99% of 79377) affected shaders:
Instrs: 37511862 -> 37495712 (-0.04%); split: -0.11%, +0.07%
CodeSize: 197990892 -> 197925104 (-0.03%); split: -0.09%, +0.06%
Latency: 261929261 -> 261273534 (-0.25%); split: -0.27%, +0.01%
InvThroughput: 43978329 -> 43921618 (-0.13%); split: -0.14%, +0.01%
VClause: 727683 -> 727695 (+0.00%); split: -0.00%, +0.00%
SClause: 1092527 -> 1092544 (+0.00%); split: -0.01%, +0.01%
VALU: 22646553 -> 22646566 (+0.00%)

Foz-DB Navi21:
Totals from 43899 (55.30% of 79377) affected shaders:
Instrs: 35649081 -> 35649110 (+0.00%); split: -0.00%, +0.00%
CodeSize: 192336212 -> 192337276 (+0.00%); split: -0.00%, +0.00%
Latency: 270621538 -> 270221431 (-0.15%); split: -0.16%, +0.02%
InvThroughput: 66757841 -> 66715918 (-0.06%); split: -0.07%, +0.01%
VClause: 734884 -> 734867 (-0.00%); split: -0.01%, +0.01%
SClause: 1072956 -> 1072951 (-0.00%); split: -0.01%, +0.01%

Foz-DB Vega10:
Totals from 52687 (83.60% of 63026) affected shaders:
Instrs: 24595280 -> 24595693 (+0.00%); split: -0.01%, +0.01%
CodeSize: 127199836 -> 127200164 (+0.00%); split: -0.01%, +0.01%
Latency: 252281578 -> 252497934 (+0.09%); split: -0.03%, +0.12%
InvThroughput: 136551527 -> 136577609 (+0.02%); split: -0.01%, +0.03%
VClause: 536798 -> 536718 (-0.01%); split: -0.04%, +0.03%
SClause: 819978 -> 819693 (-0.03%); split: -0.04%, +0.01%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
2025-01-28 17:00:45 +00:00
Georg Lehmann
068f9b51de aco/sched_ilp: use more realistic memory latencies
The last commit changes order of instructions more aggressively,
and because the memory load latencies here are wastly underestimated,
it ruins some of the work of pre-RA memory scheduling.
With the new heuristic large latency values work fine, so use them.

Foz-DB GFX1150:
Totals from 71343 (89.88% of 79377) affected shaders:
Instrs: 41627671 -> 41915029 (+0.69%); split: -0.01%, +0.70%
CodeSize: 215901308 -> 217051132 (+0.53%); split: -0.01%, +0.54%
Latency: 288714439 -> 286556159 (-0.75%); split: -0.76%, +0.02%
InvThroughput: 55834139 -> 55645301 (-0.34%); split: -0.35%, +0.01%
VClause: 829066 -> 828984 (-0.01%); split: -0.04%, +0.03%
SClause: 1237366 -> 1237448 (+0.01%); split: -0.02%, +0.02%
VALU: 23643291 -> 23643292 (+0.00%); split: -0.00%, +0.00%

Foz-DB Navi31:
Totals from 70576 (88.91% of 79377) affected shaders:
Instrs: 40928125 -> 41211820 (+0.69%); split: -0.01%, +0.70%
CodeSize: 215770956 -> 216897948 (+0.52%); split: -0.00%, +0.53%
Latency: 288139802 -> 286038405 (-0.73%); split: -0.75%, +0.02%
InvThroughput: 46391629 -> 46300275 (-0.20%); split: -0.20%, +0.01%
VClause: 829987 -> 829997 (+0.00%); split: -0.02%, +0.02%
SClause: 1229345 -> 1229425 (+0.01%); split: -0.02%, +0.02%
VALU: 24515334 -> 24515335 (+0.00%)

Foz-DB Navi21:
Instrs: 45512672 -> 45527322 (+0.03%); split: -0.01%, +0.04%
CodeSize: 244254716 -> 244311472 (+0.02%); split: -0.01%, +0.03%
Latency: 314034443 -> 311473726 (-0.82%); split: -0.83%, +0.01%
InvThroughput: 73373201 -> 73220438 (-0.21%); split: -0.21%, +0.00%
VClause: 914819 -> 914853 (+0.00%); split: -0.02%, +0.02%
SClause: 1283331 -> 1283302 (-0.00%); split: -0.01%, +0.01%

Foz-DB Vega10:
Totals from 41908 (66.49% of 63026) affected shaders:
Instrs: 22770415 -> 22779136 (+0.04%); split: -0.01%, +0.04%
CodeSize: 118195752 -> 118230540 (+0.03%); split: -0.00%, +0.03%
Latency: 242119940 -> 239665380 (-1.01%); split: -1.02%, +0.01%
InvThroughput: 131459884 -> 131182979 (-0.21%); split: -0.21%, +0.00%
VClause: 493311 -> 493215 (-0.02%); split: -0.05%, +0.03%
SClause: 758814 -> 758761 (-0.01%); split: -0.02%, +0.01%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
2025-01-28 17:00:45 +00:00
Georg Lehmann
ce897b336e aco/sched_ilp: rename priority to wait_cycles
And invert.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
2025-01-28 17:00:44 +00:00
Georg Lehmann
819938d2fa aco/sched_ilp: new latency heuristic
The main train of thought is that we should consider latency after
the write was scheduled. This means we rely a lot less on the input
order of instructions for good results.

Foz-DB GFX1150:
Totals from 75606 (95.25% of 79377) affected shaders:
Instrs: 43274326 -> 42129011 (-2.65%); split: -2.65%, +0.01%
CodeSize: 223049932 -> 218465796 (-2.06%); split: -2.06%, +0.00%
Latency: 297614199 -> 292317054 (-1.78%); split: -1.84%, +0.06%
InvThroughput: 57020160 -> 56336213 (-1.20%); split: -1.21%, +0.02%
VClause: 841775 -> 841861 (+0.01%); split: -0.06%, +0.07%
SClause: 1253516 -> 1253798 (+0.02%); split: -0.03%, +0.05%
VALU: 23893837 -> 23893828 (-0.00%); split: -0.00%, +0.00%

Foz-DB Navi31:
Totals from 75606 (95.25% of 79377) affected shaders:
Instrs: 42717592 -> 41531696 (-2.78%); split: -2.78%, +0.00%
CodeSize: 223582476 -> 218866196 (-2.11%); split: -2.11%, +0.00%
Latency: 297736383 -> 292450493 (-1.78%); split: -1.83%, +0.05%
InvThroughput: 47298730 -> 46934084 (-0.77%); split: -0.78%, +0.01%
VClause: 844982 -> 844892 (-0.01%); split: -0.07%, +0.06%
SClause: 1248433 -> 1248693 (+0.02%); split: -0.03%, +0.05%
VALU: 24819703 -> 24819704 (+0.00%); split: -0.00%, +0.00%

Foz-DB Navi21:
Totals from 76224 (96.03% of 79377) affected shaders:
Instrs: 46019515 -> 46015691 (-0.01%); split: -0.03%, +0.03%
CodeSize: 246992544 -> 246977404 (-0.01%); split: -0.03%, +0.02%
Latency: 324647457 -> 318661132 (-1.84%); split: -1.90%, +0.05%
InvThroughput: 74834800 -> 74269723 (-0.76%); split: -0.76%, +0.01%
VClause: 927601 -> 927579 (-0.00%); split: -0.04%, +0.04%
SClause: 1302666 -> 1303178 (+0.04%); split: -0.02%, +0.06%

Foz-DB Vega10:
Totals from 60142 (95.42% of 63026) affected shaders:
Instrs: 25117688 -> 25098175 (-0.08%); split: -0.10%, +0.02%
CodeSize: 129847464 -> 129769456 (-0.06%); split: -0.08%, +0.02%
Latency: 261606546 -> 262407481 (+0.31%); split: -0.12%, +0.43%
InvThroughput: 138422594 -> 138500401 (+0.06%); split: -0.03%, +0.09%
VClause: 555424 -> 555321 (-0.02%); split: -0.11%, +0.09%
SClause: 851219 -> 851620 (+0.05%); split: -0.03%, +0.08%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33222>
2025-01-28 17:00:44 +00:00
Erik Faye-Lund
0f13a42657 gallium/aux: do not assert on map-failures
The texture_map functions can fail, due to for instance address-space
exhaustion during mmap calls. Handling this by asserting turns this
into a fatal error when doing debug builds, which might not be what
users want.

Instead, let's allow this to fail. This is alredy what we do for
util_clear_color_texture and util_clear_render_target.

While we're at it, let's add some breadcrumbs to applications here, by
emitting an error at the same time. We should really consider returning
a proper pipe_error here instead, but that requires changing a lot of
function signatures, as this function are used as an implementation of
p_context::resource_copy_region()... So let's save that for later.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32431>
2025-01-28 16:17:55 +00:00
Valentine Burley
d195e411fa ci: Uprev VKCTS to 1.4.1.1
Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32817>
2025-01-28 15:01:00 +00:00
Valentine Burley
618bd07809 panvk/ci: Skip waived tests
The tests are waived in ARM waiver 4936 (see waivers.xml), so
running them in CI is unnecessary.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32817>
2025-01-28 15:01:00 +00:00