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r300: use ssa-like form for backend texture lowering
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com> Reviewed-by: Filip Gawin <None> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33066>
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1 changed files with 16 additions and 11 deletions
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@ -38,12 +38,14 @@ projective_divide(struct r300_fragment_program_compiler *compiler, struct rc_ins
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{
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struct rc_instruction *inst_mul, *inst_rcp;
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unsigned temp = rc_find_free_temporary(&compiler->Base);
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/* Make sure there is no temp reusing, some later passes depend on the SSA-like form. */
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unsigned temp_rcp = rc_find_free_temporary(&compiler->Base);
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unsigned temp_mul = rc_find_free_temporary(&compiler->Base);
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inst_rcp = rc_insert_new_instruction(&compiler->Base, inst->Prev);
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inst_rcp->U.I.Opcode = RC_OPCODE_RCP;
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inst_rcp->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_rcp->U.I.DstReg.Index = temp;
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inst_rcp->U.I.DstReg.Index = temp_rcp;
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inst_rcp->U.I.DstReg.WriteMask = RC_MASK_W;
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inst_rcp->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
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/* Because the input can be arbitrarily swizzled,
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@ -53,16 +55,16 @@ projective_divide(struct r300_fragment_program_compiler *compiler, struct rc_ins
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inst_mul = rc_insert_new_instruction(&compiler->Base, inst->Prev);
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inst_mul->U.I.Opcode = RC_OPCODE_MUL;
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inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mul->U.I.DstReg.Index = temp;
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inst_mul->U.I.DstReg.Index = temp_mul;
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inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
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inst_mul->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
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inst_mul->U.I.SrcReg[1].Index = temp;
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inst_mul->U.I.SrcReg[1].Index = temp_rcp;
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inst_mul->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_WWWW;
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reset_srcreg(&inst->U.I.SrcReg[0]);
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inst->U.I.Opcode = RC_OPCODE_TEX;
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inst->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
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inst->U.I.SrcReg[0].Index = temp;
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inst->U.I.SrcReg[0].Index = temp_mul;
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}
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/**
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@ -152,33 +154,36 @@ radeonTransformTEX(struct radeon_compiler *c, struct rc_instruction *inst, void
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unsigned two, two_swizzle;
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inst_mul = rc_insert_new_instruction(c, inst->Prev);
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unsigned temp_mul = rc_find_free_temporary(c);
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inst_mul->U.I.Opcode = RC_OPCODE_MUL;
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inst_mul->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mul->U.I.DstReg.Index = temp;
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inst_mul->U.I.DstReg.Index = temp_mul;
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inst_mul->U.I.DstReg.WriteMask = RC_MASK_XYZ;
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inst_mul->U.I.SrcReg[0] = inst->U.I.SrcReg[0];
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inst_mul->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_HHHH;
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inst_frc = rc_insert_new_instruction(c, inst->Prev);
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unsigned temp_frc = rc_find_free_temporary(c);
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inst_frc->U.I.Opcode = RC_OPCODE_FRC;
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inst_frc->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_frc->U.I.DstReg.Index = temp;
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inst_frc->U.I.DstReg.Index = temp_frc;
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inst_frc->U.I.DstReg.WriteMask = RC_MASK_XYZ;
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inst_frc->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
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inst_frc->U.I.SrcReg[0].Index = temp;
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inst_frc->U.I.SrcReg[0].Index = temp_mul;
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inst_frc->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZ0;
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two = rc_constants_add_immediate_scalar(&c->Program.Constants, 2, &two_swizzle);
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inst_mad = rc_insert_new_instruction(c, inst->Prev);
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unsigned temp_mad = rc_find_free_temporary(c);
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inst_mad->U.I.Opcode = RC_OPCODE_MAD;
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inst_mad->U.I.DstReg.File = RC_FILE_TEMPORARY;
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inst_mad->U.I.DstReg.Index = temp;
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inst_mad->U.I.DstReg.Index = temp_mad;
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inst_mad->U.I.DstReg.WriteMask = RC_MASK_XYZ;
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inst_mad->U.I.SrcReg[0].File = RC_FILE_TEMPORARY;
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inst_mad->U.I.SrcReg[0].Index = temp;
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inst_mad->U.I.SrcReg[0].Index = temp_frc;
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inst_mad->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_XYZ0;
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inst_mad->U.I.SrcReg[1].File = RC_FILE_CONSTANT;
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inst_mad->U.I.SrcReg[1].Index = two;
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@ -194,7 +199,7 @@ radeonTransformTEX(struct radeon_compiler *c, struct rc_instruction *inst, void
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inst_add->U.I.DstReg.WriteMask = RC_MASK_XYZ;
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inst_add->U.I.SrcReg[0].Swizzle = RC_SWIZZLE_1111;
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inst_add->U.I.SrcReg[1].File = RC_FILE_TEMPORARY;
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inst_add->U.I.SrcReg[1].Index = temp;
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inst_add->U.I.SrcReg[1].Index = temp_mad;
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inst_add->U.I.SrcReg[1].Swizzle = RC_SWIZZLE_XYZ0;
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inst_add->U.I.SrcReg[1].Abs = 1;
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inst_add->U.I.SrcReg[1].Negate = RC_MASK_XYZ;
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