Commit graph

67027 commits

Author SHA1 Message Date
Karol Herbst
767695b2c4 asahi: implement get_cl_cts_version
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31589>
2024-10-10 18:24:31 +00:00
Jose Maria Casanova Crespo
687ed3fcaa v3d: initialize job local key with the 8 color buffer available in v7.1+
Fixes: 9e90d95508 ("v3d,v3dv: support up to 8 render targets in v7.1+")

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31582>
2024-10-10 16:44:58 +00:00
Daniel Stone
3e7c9aad8a ci/virgl: Fix library path
We need to set $LD_LIBRARY_PATH so we can find GL/Vulkan at all, and
$LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI modules.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
4e3e84c240 ci/zink: Fix library path
We need to set $LD_LIBRARY_PATH so we can find GL at all, and
$LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI modules.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
61f5178f6e ci/swrast: Archive Xvfb logs
If anything goes wrong, it's useful to have actual output, as opposed to
guessing from the void.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Daniel Stone
8b594d29b6 ci/swrast: Fix library paths for llvmpipe/softpipe
We need to set $LIBGL_DRIVERS_PATH so Xvfb will pick up the correct DRI
modules. We were setting $LD_LIBRARY_PATH, but llvmpipe was getting it
wrong, so Weston was picking up the host GLES, which we're about to no
longer install.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31281>
2024-10-10 11:05:57 +00:00
Erik Faye-Lund
cf71e5534b i915: do not calculate native instructions
This isn't wired up anywhere, so let's just drop it.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31538>
2024-10-10 09:36:43 +00:00
David Rosca
3c5fe03b92 radeonsi/vcn: Add support for VCN5 dpb tier2
Co-authored-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
1e1f078099 radeonsi/vcn: Add support for VCN5 AV1 compound
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
05f7589fec radeonsi/vcn: Fix coded size in sequence header on VCN5
Introduce coded_width/coded_height for values used in headers
and change it to aligned size on VCN4 to reflect the actual coded size.
VCN5 doesn't have this limitation and can code any size.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
8b2f0fb574 radeonsi/vcn: Support raw packed headers for AV1
Same as H264/HEVC, we still write sequence header ourselves
and slice header is sent to FW, everything else gets copied
directly to output bitstream buffer.
Fixes generating correct output with libva-utils/av1encode.
Also fixes temporal delimiter insertion, it's no longer forced
on every frame, but instead it lets application handle it.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:21 +00:00
David Rosca
46d8e57f16 frontends/va: Remove now unused ref fields for AV1 encode
Need to get rid of these as they allocate buffers for drivers
not implementing create_dpb_buffer and waste memory.
No driver is using these fields anymore.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
813812b925 radeonsi/vcn: Switch to app DPB management for AV1
Also move the common part of the frame header into shared function.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
454a26662d frontends/va: Support raw packed headers for AV1
When there is show_existing_frame = 1 frame header, we don't parse
it and instead output directly as raw header. Only the frame header
that will be used for encoding current frame is parsed and indicated
with is_slice.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
1fdd773450 frontends/va: Parse more AV1 frame and sequence header params
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
David Rosca
36ddcc130b frontends/va: Implement DPB management for AV1
Same logic as H264 and HEVC, except surfaces are evicted immediately.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31520>
2024-10-10 09:02:20 +00:00
Christian Gmeiner
3ae3425c5d etnaviv: blt: Convert assert to real if
etna_try_blt_blit(..) returns if it is possible to do the blit
in hardware or not. When building mesa in debug mode this assert(..)
is hit many times.

Fixes the following piglits on GC7000L:
 - spec@!opengl 1.0@gl-1.0-scissor-copypixels
 - spec@nv_conditional_render@copypixels
 - spec@!opengl 1.1@copypixels-draw-sync
 - spec@!opengl 1.1@copypixels-sync
 - spec@!opengl 1.1@depthstencil-default_fb-blit
 - spec@!opengl 1.1@draw-copypixels-sync
 - spec@!opengl 1.1@gl-1.1-xor-copypixels

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31581>
2024-10-10 08:31:53 +00:00
David Rosca
20d5020ad7 radeonsi/vcn: Fix out of bounds read in H264 decode
When all 16 references are used, this would read pic->ref[16].
Same for HEVC, but HEVC only uses 15 reference frames so it would
never happen there yet is still reported by coverity.

Fixes coverity issues 1497283 and 1465569 Out-of-bounds read

Cc: mesa-stable

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:36 +00:00
David Rosca
10a7356488 radeonsi/vcn: Fix out of bounds write when invalidating QP map regions
Fixes coverity issue 1559460 Out-of-bounds write

Fixes: 9c07a2e10d ("radeonsi/vcn: ROI feature implementation")

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:35 +00:00
David Rosca
17842f0584 radeonsi/vcn: Fix some small coverity issues
* 1619409 Resource leak
  - fix leak when mapping encode bitstream buffer fails
* 1619403 Dereference after null check
  - remove size ptr NULL check in radeon_enc_get_feedback, can't be NULL
* 1434887 Out-of-bounds access
  - use correct variable for memset in get_vp9_msg
* 1619400 'Constant' variable guards dead code
  - remove code handling frame_mbs_only_flag == 0, hardcoded to true

Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31558>
2024-10-10 06:25:35 +00:00
Guilherme Gallo
59d909eb56 ci/lava: Make perf jobs use pyutils artifact
Following the merge of Merge Request #31151, we encountered an issue
where the performance jobs were failing silently. Although these
failures did not cause the pipeline to fail, they resulted in warnings
for all merge requests that ran the .*-traces-performance jobs, putting
critical performance data for the [Mesa Performance Driver
dashboard](https://ci-stats-grafana.freedesktop.org/goto/G3xkvykHg?orgId=1)
at risk.

To resolve this issue, this commit updates the LAVA performance jobs to
utilize the Pyutils artifact package, which is now the only required
artifact for the jobs that run the LAVA job submitter.

Fixes: dd5d737e6c ("ci/lava: Use new pyutils container")

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31553>
2024-10-10 01:33:16 +00:00
Rob Clark
753c8bf834 freedreno/a6xx: Emit CP_SET_AMBLE packets
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
d572fcf04a freedreno/a6xx: Move more state emit per-bin
With skipsaverestore=1 we can't rely on this values being restored.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
270e595811 freedreno/a6xx: Move static regs to preamble IB
We can re-use this for preemption.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
0c36ca7446 freedreno/a6xx: Move PC_TESSFACTOR_ADDR emit
This depends on batch state, so emit in gmem code.  The remainder of the
static reg initialization can be re-used across batches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
f3cc9335e6 freedreno/a6xx: Set bin size per bin
It is not saved/restored by level 1 preemption with skipsaverestore=1,
so we need to set it for each bin.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
be6342633c freedreno/a6xx: Cleanup WFIs around RB_CCU_CNTL
This was only actually needed on the earliest a6xx (probably just
a630?).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
3aac51a6d5 freedreno/a6xx: De-open-code VFD_MODE_CNTL
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Rob Clark
2f82555efa freedreno/a6xx: Only emit VFD/PC_POWER_CNTL for a6xx
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:46 +00:00
Jonathan Marek
b6432a6c66 freedreno/a6xx: add missing USES_GMEM flag and BIN_RENDER_END markers
Add USES_GMEM flag to indicate that GMEM is in use, so that preemption can
know it needs save and restore GMEM contents.

The missing BIN_RENDER_END markers are also added, their purpose is to
clear the USES_GMEM flag once GMEM is no longer in use.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Jonathan Marek
72900e1aac freedreno: improve a6xx CP_SET_MARKER xml definition
Use real names for most of a6xx_marker enum, add USES_GMEM, remove
overlapping bitfields.

Note the actual "real names" start with PM4_RENDER_MODE_ instead of RM6_

This is a small change to adreno_pm4.xml, with the corresponding
find/replace and updated ci references

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
2024-10-10 00:50:45 +00:00
Lionel Landwerlin
e4d1fd7fd6 iris: delete stencil mapping support
Now that we have ISL support.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00
Maíra Canal
47a78614ea v3d: Don't use performance counters names array with an older kernel
Starting with Linux v6.11+, performance counter information is no
longer duplicated in both the kernel and userspace. Instead, an IOCTL
retrieves this information, allowing userspace to maintain a local
array for reuse, thus avoiding redundant kernel queries.

However, support for older kernels without these new IOCTLs remains.
To distinguish between versions, we check `devinfo->max_perfcnt` -
which is non-zero on Linux v6.11+ and zero on older kernels.

Currently, applications using performance queries on platforms with
older kernels encounter a SEGFAULT, as we don't validate
`devinfo->max_perfcnt` before accessing the userspace array for
performance counter information.

This commit makes sure that, if `devinfo->max_perfcnt` is zero,
`screen->perfcnt_names` will be NULL. This way, we can check if
`screen->perfcnt_names` is different than NULL before attempting to use
the userspace array.

Fixes: 017dde0d1c ("v3d: Use DRM_IOCTL_V3D_GET_COUNTER to get perfcnt information")
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31552>
2024-10-09 15:51:51 -03:00
Zhang He
5d7f3753d7 iris, crocus: fix a typo and break comment line correctly
Signed-off-by: Zhang He <zhanghe9702@163.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31557>
2024-10-09 17:56:23 +00:00
Christian Gmeiner
04521c14b0 etnaviv: Improve split sampler check
Check if the block size is bigger then 64. We want to block
e.g. one of the following formats:
 - R32G32B32A32_FLOAT
 - R32G32B32A32_SINT
 - R32G32B32A32_ZINT

Unbreaks e.g. dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb16i

Fixes: e481c1269c ("etnaviv: disable 64bpp render/sampler formats")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27111>
2024-10-09 15:17:33 +00:00
David Rosca
89ea2b6c26 radeonsi/vcn: Don't hardcode nal_ref_idc
For slice header use the value parsed by frontend.
For SPS and PPS directly output first NAL byte from packed header.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
2024-10-08 15:24:36 +00:00
David Rosca
8880f0f141 radeonsi/vcn: Use correct initial DPB size for HEVC encode
sps_max_dec_pic_buffering_minus1 specifies the maximum number of
references, same as H264 max_num_ref_frames.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
2024-10-08 15:24:36 +00:00
David Rosca
88c134d496 radeonsi/vcn: Allow per-frame QP and max frame size changes
Also don't reset QP values when rate control changes because
QP is ignored with rate control enabled anyway.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
2024-10-08 15:24:36 +00:00
Lucas Stach
a422ebc500 etnaviv: flush shader caches when UBO content is modified
Shader load/stores are cached by the shader L1 cache. As UBOs on etnaviv
are implemented as regular loads from the constant buffer, this cache
needs to be flushed whenever the content of a constant buffer is modified.

Fixes most of the currently failing dEQP-GLES3.functional.ubo.* on GC3000.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31527>
2024-10-08 10:32:16 +00:00
Tapani Pälli
3e29ea69ce iris: add depth, DC and L3 fabric flush for aux map invalidation
These should be included according to table in Bspec 43904.

Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
2024-10-08 08:45:40 +00:00
Tapani Pälli
11774075a3 iris: add plumbing/support for L3 fabric flush
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
2024-10-08 08:45:40 +00:00
Peyton Lee
0dacdba804 radeonsi: correct map and unmap function timing
The timing of buffer map and unmap is wrong.
Correct the usage of map and unmap function.

Signed-off-by: Peyton Lee <peytolee@amd.com>
2024-10-08 13:44:24 +08:00
Mike Blumenkrantz
e46dffddb1 util/vbuf: rename/consolidate some bools
now that the pipe caps are unified, this makes reading a bit easier

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31482>
2024-10-07 13:09:59 +00:00
Mike Blumenkrantz
d008aaa6da gallium: rework vbuf alignment pipe caps
this consolidates 4 pipe caps into 1 using an enum

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Neha Bhende <neha.bhende@broadcom.com>

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31482>
2024-10-07 13:09:59 +00:00
Samuel Pitoiset
afe28429f9 zink/ci: update list of expected failures for NAVI10
Looks like this test is also fixed on NAVI10.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31543>
2024-10-07 12:33:41 +00:00
Erico Nunes
b274e32de3 lima/ci: update piglit ci expectations
Some tests were affected during lima lab downtime.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31537>
2024-10-06 09:54:30 +00:00
Erico Nunes
e60c735594 lima/ci: define FDO_HTTP_CACHE_URI for caching-proxy
This did not use to exist in the lima lab, but it does now.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31537>
2024-10-06 09:54:30 +00:00
Karol Herbst
1301d61de4 rusticl: allow devices to be enabled by default
Reviewed-by: David Heidelberg <david@ixit.cz>
Acked-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31202>
2024-10-05 22:13:12 +00:00
Alyssa Rosenzweig
9845e01f0f asahi,hk: implement remapping in epilog
for DRLR

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31532>
2024-10-05 18:30:13 +00:00
Alyssa Rosenzweig
1d195b2074 asahi: optimize !robust VBO
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31532>
2024-10-05 18:30:13 +00:00