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iris: add plumbing/support for L3 fabric flush

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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
This commit is contained in:
Tapani Pälli 2024-08-28 07:23:15 +03:00 • committed by Marge Bot
parent e3814dee1a
commit 11774075a3
3 changed files with 5 additions and 1 deletions
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1
src/gallium/drivers/iris/iris_context.h
View file

@ -499,6 +499,7 @@ enum pipe_control_flags
PIPE_CONTROL_L3_READ_ONLY_CACHE_INVALIDATE = (1 << 28),
PIPE_CONTROL_UNTYPED_DATAPORT_CACHE_FLUSH = (1 << 29),
PIPE_CONTROL_CCS_CACHE_FLUSH = (1 << 30),
PIPE_CONTROL_L3_FABRIC_FLUSH = (1 << 31),
};
#define PIPE_CONTROL_CACHE_FLUSH_BITS \

4
src/gallium/drivers/iris/iris_state.c
View file

@ -9980,7 +9980,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
if (INTEL_DEBUG(DEBUG_PIPE_CONTROL)) {
fprintf(stderr,
" PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n",
" PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n",
(flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "",
(flags & PIPE_CONTROL_CS_STALL) ? "CS " : "",
(flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) ? "Scoreboard " : "",
@ -9991,6 +9991,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
(flags & PIPE_CONTROL_DATA_CACHE_FLUSH) ? "DC " : "",
(flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH) ? "ZFlush " : "",
(flags & PIPE_CONTROL_TILE_CACHE_FLUSH) ? "Tile " : "",
(flags & PIPE_CONTROL_L3_FABRIC_FLUSH) ? "L3Fabric " : "",
(flags & PIPE_CONTROL_CCS_CACHE_FLUSH) ? "CCS " : "",
(flags & PIPE_CONTROL_DEPTH_STALL) ? "ZStall " : "",
(flags & PIPE_CONTROL_STATE_CACHE_INVALIDATE) ? "State " : "",
@ -10025,6 +10026,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
#endif
#if GFX_VER == 12
pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH;
pc.L3FabricFlush = flags & PIPE_CONTROL_L3_FABRIC_FLUSH;
#endif
#if GFX_VER > 11
pc.HDCPipelineFlushEnable = flags & PIPE_CONTROL_FLUSH_HDC;

1
src/gallium/drivers/iris/iris_utrace.c
View file

@ -237,6 +237,7 @@ iris_utrace_pipe_flush_bit_to_ds_stall_flag(uint32_t flags)
{ .iris = PIPE_CONTROL_DEPTH_CACHE_FLUSH, .ds = INTEL_DS_DEPTH_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_DATA_CACHE_FLUSH, .ds = INTEL_DS_DATA_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_TILE_CACHE_FLUSH, .ds = INTEL_DS_TILE_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_L3_FABRIC_FLUSH, .ds = INTEL_DS_L3_FABRIC_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_RENDER_TARGET_FLUSH, .ds = INTEL_DS_RENDER_TARGET_CACHE_FLUSH_BIT, },
{ .iris = PIPE_CONTROL_STATE_CACHE_INVALIDATE, .ds = INTEL_DS_STATE_CACHE_INVALIDATE_BIT, },
{ .iris = PIPE_CONTROL_CONST_CACHE_INVALIDATE, .ds = INTEL_DS_CONST_CACHE_INVALIDATE_BIT, },