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https://gitlab.freedesktop.org/mesa/mesa.git
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radeonsi/vcn: ROI feature implementation
Implemented ROI feature in VCN generations. Reviewed-by: Boyuan Zhang <boyuan.zhang@amd.com> Signed-off-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26659>
This commit is contained in:
Ruijing Dong
Marge Bot
parent
d6da63071e
commit
9c07a2e10d
5 changed files with 189 additions and 13 deletions
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@ -63,12 +63,25 @@ static uint32_t radeon_vcn_per_frame_frac(uint32_t bitrate, uint32_t den, uint32
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return (uint32_t)((remainder << 32) / num);
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}
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/* block length for av1 and hevc is the same, 64, for avc 16 */
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static uint32_t radeon_vcn_enc_blocks_in_frame(struct radeon_encoder *enc,
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uint32_t *width_in_block,
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uint32_t *height_in_block)
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{
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bool is_h264 = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC;
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uint32_t block_length = is_h264 ? PIPE_H264_MB_SIZE : PIPE_H265_ENC_CTB_SIZE;
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*width_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.width, block_length);
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*height_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.height, block_length);
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return block_length;
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}
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static void radeon_vcn_enc_get_intra_refresh_param(struct radeon_encoder *enc,
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bool need_filter_overlap,
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struct pipe_enc_intra_refresh *intra_refresh)
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{
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bool is_h264;
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uint32_t block_length, width_in_block, height_in_block;
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uint32_t width_in_block, height_in_block;
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enc->enc_pic.intra_refresh.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE;
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/* some exceptions where intra-refresh is disabled:
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@ -82,11 +95,7 @@ static void radeon_vcn_enc_get_intra_refresh_param(struct radeon_encoder *enc,
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return;
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}
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is_h264 = u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC;
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/* hevc and av1 are sharing the same alignment size 64 */
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block_length = is_h264 ? PIPE_H264_MB_SIZE : PIPE_H265_ENC_CTB_SIZE;
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width_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.width, block_length);
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height_in_block = PIPE_ALIGN_IN_BLOCK_SIZE(enc->base.height, block_length);
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radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
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switch(intra_refresh->mode) {
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case INTRA_REFRESH_MODE_UNIT_ROWS:
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@ -121,6 +130,62 @@ static void radeon_vcn_enc_get_intra_refresh_param(struct radeon_encoder *enc,
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}
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}
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static void radeon_vcn_enc_get_roi_param(struct radeon_encoder *enc,
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struct pipe_enc_roi *roi)
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{
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bool is_av1 = u_reduce_video_profile(enc->base.profile)
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== PIPE_VIDEO_FORMAT_AV1;
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if (!roi->num)
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enc->enc_pic.enc_qp_map.qp_map_type = RENCODE_QP_MAP_TYPE_NONE;
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else {
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uint32_t width_in_block, height_in_block;
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uint32_t block_length;
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int32_t i, j, pa_format = 0;
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/* rate control is using a different qp map type */
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if (enc->enc_pic.rc_session_init.rate_control_method) {
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enc->enc_pic.enc_qp_map.qp_map_type = RENCODE_QP_MAP_TYPE_MAP_PA;
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pa_format = 1;
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}
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else
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enc->enc_pic.enc_qp_map.qp_map_type = RENCODE_QP_MAP_TYPE_DELTA;
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block_length = radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
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for (i = RENCODE_QP_MAP_MAX_REGIONS; i >= roi->num; i--)
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enc->enc_pic.enc_qp_map.map[i].is_valid = false;
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/* reverse the map sequence */
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for (j = 0; i >= 0; i--, j++) {
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struct rvcn_enc_qp_map_region *map = &enc->enc_pic.enc_qp_map.map[j];
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struct pipe_enc_region_in_roi *region = &roi->region[i];
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map->is_valid = region->valid;
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if (region->valid) {
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int32_t av1_qi_value;
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/* mapped av1 qi into the legacy qp range by dividing by 5 and
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* rounding up in any rate control mode.
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*/
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if (is_av1 && pa_format) {
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if (region->qp_value > 0)
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av1_qi_value = (region->qp_value + 2) / 5;
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else if (region->qp_value < 0)
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av1_qi_value = (region->qp_value - 2) / 5;
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else
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av1_qi_value = region->qp_value;
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map->qp_delta = av1_qi_value;
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} else
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map->qp_delta = region->qp_value;
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map->x_in_unit = CLAMP((region->x / block_length), 0, width_in_block - 1);
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map->y_in_unit = CLAMP((region->y / block_length), 0, height_in_block - 1);
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map->width_in_unit = CLAMP((region->width / block_length), 0, width_in_block);
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map->height_in_unit = CLAMP((region->height / block_length), 0, width_in_block);
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}
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}
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}
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}
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static void radeon_vcn_enc_h264_get_cropping_param(struct radeon_encoder *enc,
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struct pipe_h264_enc_picture_desc *pic)
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{
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@ -368,6 +433,7 @@ static void radeon_vcn_enc_h264_get_param(struct radeon_encoder *enc,
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use_filter = enc->enc_pic.h264_deblock.disable_deblocking_filter_idc != 1;
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radeon_vcn_enc_get_intra_refresh_param(enc, use_filter, &pic->intra_refresh);
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radeon_vcn_enc_get_roi_param(enc, &pic->roi);
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}
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static void radeon_vcn_enc_hevc_get_cropping_param(struct radeon_encoder *enc,
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@ -582,6 +648,7 @@ static void radeon_vcn_enc_hevc_get_param(struct radeon_encoder *enc,
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radeon_vcn_enc_get_intra_refresh_param(enc,
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!(enc->enc_pic.hevc_deblock.deblocking_filter_disabled),
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&pic->intra_refresh);
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radeon_vcn_enc_get_roi_param(enc, &pic->roi);
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}
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static void radeon_vcn_enc_av1_get_spec_misc_param(struct radeon_encoder *enc,
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@ -729,6 +796,7 @@ static void radeon_vcn_enc_av1_get_param(struct radeon_encoder *enc,
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radeon_vcn_enc_get_intra_refresh_param(enc,
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true,
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&pic->intra_refresh);
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radeon_vcn_enc_get_roi_param(enc, &pic->roi);
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}
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static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
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@ -904,6 +972,70 @@ static int setup_dpb(struct radeon_encoder *enc)
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return offset;
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}
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/* each block (MB/CTB/SB) has one QP/QI value */
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static uint32_t roi_buffer_size(struct radeon_encoder *enc)
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{
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uint32_t width_in_block, height_in_block;
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radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
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return width_in_block * height_in_block * sizeof(uint32_t);
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}
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static void arrange_qp_map(uint32_t *start,
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struct rvcn_enc_qp_map_region *map,
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uint32_t width_in_block,
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uint32_t height_in_block)
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{
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uint32_t i, j;
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uint32_t offset;
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uint32_t num_in_x = MIN2(map->x_in_unit + map->width_in_unit, width_in_block)
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- map->x_in_unit;
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uint32_t num_in_y = MIN2(map->y_in_unit + map->height_in_unit, height_in_block)
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- map->y_in_unit;;
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for (j = 0; j < num_in_y; j++) {
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for (i = 0; i < num_in_x; i++) {
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offset = map->x_in_unit + i + (map->y_in_unit + j) * width_in_block;
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*(start + offset) = (int32_t)map->qp_delta;
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}
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}
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}
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/* Arrange roi map values according to the input regions.
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* The arrangment will consider the lower sequence region
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* higher priority and that could overlap the higher sequence
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* map region. */
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static int generate_roi_map(struct radeon_encoder *enc)
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{
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uint32_t width_in_block, height_in_block;
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uint32_t i;
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uint32_t *p_roi = NULL;
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radeon_vcn_enc_blocks_in_frame(enc, &width_in_block, &height_in_block);
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assert (enc->roi_size >= width_in_block * height_in_block);
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p_roi = (uint32_t *)enc->ws->buffer_map(enc->ws,
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enc->roi->res->buf,
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&enc->cs,
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PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
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if (!p_roi)
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goto error;
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memset(p_roi, 0, width_in_block * height_in_block * sizeof(uint32_t));
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for (i = 0; i < ARRAY_SIZE(enc->enc_pic.enc_qp_map.map); i++) {
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struct rvcn_enc_qp_map_region *map = &enc->enc_pic.enc_qp_map.map[i];
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if (map->is_valid)
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arrange_qp_map(p_roi, map, width_in_block, height_in_block);
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}
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enc->ws->buffer_unmap(enc->ws, enc->roi->res->buf);
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return 0;
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error:
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return -1;
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}
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static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
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struct pipe_video_buffer *source,
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struct pipe_picture_desc *picture)
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@ -951,6 +1083,23 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
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}
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}
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/* qp map buffer could be created here, and release at the end */
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if (enc->enc_pic.enc_qp_map.qp_map_type != RENCODE_QP_MAP_TYPE_NONE) {
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if (!enc->roi) {
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enc->roi = CALLOC_STRUCT(rvid_buffer);
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enc->roi_size = roi_buffer_size(enc);
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if (!enc->roi || !enc->roi_size ||
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!si_vid_create_buffer(enc->screen, enc->roi, enc->roi_size, PIPE_USAGE_DYNAMIC)) {
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RVID_ERR("Can't create ROI buffer.\n");
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goto error;
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}
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}
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if(generate_roi_map(enc)) {
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RVID_ERR("Can't form roi map.\n");
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goto error;
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}
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}
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if (source->buffer_format == PIPE_FORMAT_NV12 ||
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source->buffer_format == PIPE_FORMAT_P010 ||
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source->buffer_format == PIPE_FORMAT_P016) {
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@ -989,6 +1138,7 @@ error:
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->dpb);
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->si);
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->cdf);
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->roi);
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}
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static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
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@ -1047,6 +1197,7 @@ static void radeon_enc_destroy(struct pipe_video_codec *encoder)
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->dpb);
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->cdf);
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RADEON_ENC_DESTROY_VIDEO_BUFFER(enc->roi);
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enc->ws->cs_destroy(&enc->cs);
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if (enc->ectx)
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enc->ectx->destroy(enc->ectx);
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@ -1070,8 +1221,7 @@ static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feed
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enc->ws->buffer_unmap(enc->ws, fb->res->buf);
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}
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si_vid_destroy_buffer(fb);
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FREE(fb);
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RADEON_ENC_DESTROY_VIDEO_BUFFER(fb);
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}
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static void radeon_enc_destroy_fence(struct pipe_video_codec *encoder,
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@ -172,6 +172,7 @@ struct radeon_enc_pic {
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rvcn_enc_stats_t enc_statistics;
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rvcn_enc_input_format_t enc_input_format;
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rvcn_enc_output_format_t enc_output_format;
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rvcn_enc_qp_map_t enc_qp_map;
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};
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struct radeon_encoder {
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@ -206,6 +207,7 @@ struct radeon_encoder {
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void (*rc_per_pic)(struct radeon_encoder *enc);
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void (*encode_params)(struct radeon_encoder *enc);
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void (*encode_params_codec_spec)(struct radeon_encoder *enc);
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void (*qp_map)(struct radeon_encoder *enc);
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void (*op_init)(struct radeon_encoder *enc);
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void (*op_close)(struct radeon_encoder *enc);
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void (*op_enc)(struct radeon_encoder *enc);
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@ -242,6 +244,7 @@ struct radeon_encoder {
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struct rvid_buffer *fb;
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struct rvid_buffer *dpb;
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struct rvid_buffer *cdf;
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struct rvid_buffer *roi;
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struct radeon_enc_pic enc_pic;
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struct pb_buffer *stats;
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rvcn_enc_cmd_t cmd;
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@ -260,6 +263,7 @@ struct radeon_encoder {
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bool emulation_prevention;
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bool need_feedback;
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unsigned dpb_size;
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unsigned roi_size;
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rvcn_enc_picture_info_t dpb_info[RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES];
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unsigned max_ltr_idx;
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@ -34,6 +34,7 @@
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#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x0000000e
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#define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000010
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#define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU 0x00000020
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#define RENCODE_IB_PARAM_QP_MAP 0x00000021
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#define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000024
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#define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL 0x00100001
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@ -718,7 +719,8 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
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radeon_enc_code_se(enc, 0x0);
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radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
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radeon_enc_code_fixed_bits(enc, 0x0, 1);
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if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
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if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
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enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
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radeon_enc_code_fixed_bits(enc, 0x0, 1);
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else {
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radeon_enc_code_fixed_bits(enc, 0x1, 1);
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@ -1268,6 +1270,19 @@ static void radeon_enc_encode_statistics(struct radeon_encoder *enc)
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RADEON_ENC_END();
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}
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static void radeon_enc_qp_map(struct radeon_encoder *enc)
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{
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if (enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
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return;
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enc->enc_pic.enc_qp_map.qp_map_pitch = 0;
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RADEON_ENC_BEGIN(enc->cmd.enc_qp_map);
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RADEON_ENC_CS(enc->enc_pic.enc_qp_map.qp_map_type);
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RADEON_ENC_READWRITE(enc->roi->res->buf, enc->roi->res->domains, 0);
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RADEON_ENC_CS(enc->enc_pic.enc_qp_map.qp_map_pitch);
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RADEON_ENC_END();
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}
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static void radeon_enc_op_init(struct radeon_encoder *enc)
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{
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RADEON_ENC_BEGIN(RENCODE_IB_OP_INITIALIZE);
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@ -1385,6 +1400,7 @@ static void encode(struct radeon_encoder *enc)
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enc->bitstream(enc);
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enc->feedback(enc);
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enc->intra_refresh(enc);
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enc->qp_map(enc);
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enc->op_preset(enc);
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enc->op_enc(enc);
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@ -1544,6 +1560,7 @@ void radeon_enc_1_2_init(struct radeon_encoder *enc)
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enc->session_init = radeon_enc_session_init;
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enc->encode_statistics = radeon_enc_encode_statistics;
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enc->nalu_aud = radeon_enc_nalu_aud;
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enc->qp_map = radeon_enc_qp_map;
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if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
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enc->slice_control = radeon_enc_slice_control;
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@ -1591,6 +1608,7 @@ void radeon_enc_1_2_init(struct radeon_encoder *enc)
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enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
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enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
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enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
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enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
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enc->enc_pic.session_info.interface_version =
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((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
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@ -34,6 +34,7 @@
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#define RENCODE_IB_PARAM_INTRA_REFRESH 0x00000010
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#define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER 0x00000011
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#define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER 0x00000012
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#define RENCODE_IB_PARAM_QP_MAP 0x00000014
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#define RENCODE_IB_PARAM_FEEDBACK_BUFFER 0x00000015
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#define RENCODE_IB_PARAM_ENCODE_STATISTICS 0x00000019
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@ -399,7 +400,8 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
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radeon_enc_code_se(enc, 0x0);
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
|
||||
radeon_enc_code_fixed_bits(enc, 0x0, 1);
|
||||
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
|
||||
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
|
||||
enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
|
||||
radeon_enc_code_fixed_bits(enc, 0x0, 1);
|
||||
else {
|
||||
radeon_enc_code_fixed_bits(enc, 0x1, 1);
|
||||
|
|
@ -514,6 +516,7 @@ static void encode(struct radeon_encoder *enc)
|
|||
enc->feedback(enc);
|
||||
enc->encode_statistics(enc);
|
||||
enc->intra_refresh(enc);
|
||||
enc->qp_map(enc);
|
||||
enc->input_format(enc);
|
||||
enc->output_format(enc);
|
||||
|
||||
|
|
@ -565,6 +568,7 @@ void radeon_enc_2_0_init(struct radeon_encoder *enc)
|
|||
enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
|
||||
enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
|
||||
enc->cmd.enc_statistics = RENCODE_IB_PARAM_ENCODE_STATISTICS;
|
||||
enc->cmd.enc_qp_map = RENCODE_IB_PARAM_QP_MAP;
|
||||
|
||||
enc->enc_pic.session_info.interface_version =
|
||||
((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
|
||||
|
|
|
|||
|
|
@ -403,8 +403,8 @@ static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
|
|||
radeon_enc_code_se(enc, 0x0);
|
||||
radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
|
||||
radeon_enc_code_fixed_bits(enc, 0x1, 1);
|
||||
if (enc->enc_pic.rc_session_init.rate_control_method ==
|
||||
RENCODE_RATE_CONTROL_METHOD_NONE)
|
||||
if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE &&
|
||||
enc->enc_pic.enc_qp_map.qp_map_type == RENCODE_QP_MAP_TYPE_NONE)
|
||||
radeon_enc_code_fixed_bits(enc, 0x0, 1);
|
||||
else {
|
||||
radeon_enc_code_fixed_bits(enc, 0x1, 1);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue