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radeonsi/vcn: Allow per-frame QP and max frame size changes

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Also don't reset QP values when rate control changes because
QP is ignored with rate control enabled anyway.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31354>
This commit is contained in:
David Rosca 2024-09-23 09:07:39 +02:00 • committed by Marge Bot
parent 85d7826afa
commit 88c134d496
1 changed files with 11 additions and 23 deletions
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34
src/gallium/drivers/radeonsi/radeon_vcn_enc.c
View file

@ -1350,16 +1350,11 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
(enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rate_ctrl[0].frame_rate_num) ||
(enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rate_ctrl[0].frame_rate_den);
if (enc->need_rate_control) {
enc->enc_pic.rc_per_pic.qp_i = 0;
enc->enc_pic.rc_per_pic.qp_p = 0;
enc->enc_pic.rc_per_pic.qp_b = 0;
}
enc->need_rc_per_pic =
(!enc->enc_pic.rc_per_pic.qp_i && enc->enc_pic.rc_per_pic.qp_i != pic->quant_i_frames) ||
(!enc->enc_pic.rc_per_pic.qp_p && enc->enc_pic.rc_per_pic.qp_p != pic->quant_p_frames) ||
(!enc->enc_pic.rc_per_pic.qp_b && enc->enc_pic.rc_per_pic.qp_b != pic->quant_b_frames) ||
(enc->enc_pic.rc_per_pic.qp_i != pic->quant_i_frames) ||
(enc->enc_pic.rc_per_pic.qp_p != pic->quant_p_frames) ||
(enc->enc_pic.rc_per_pic.qp_b != pic->quant_b_frames) ||
(enc->enc_pic.rc_per_pic.max_au_size_i != pic->rate_ctrl[0].max_au_size) ||
(enc->enc_pic.rc_per_pic.qvbr_quality_level != pic->rate_ctrl[0].vbr_quality_factor);
} else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
@ -1369,14 +1364,10 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
(enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rc[0].frame_rate_num) ||
(enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rc[0].frame_rate_den);
if (enc->need_rate_control) {
enc->enc_pic.rc_per_pic.qp_i = 0;
enc->enc_pic.rc_per_pic.qp_p = 0;
}
enc->need_rc_per_pic =
(!enc->enc_pic.rc_per_pic.qp_i && enc->enc_pic.rc_per_pic.qp_i != pic->rc[0].quant_i_frames) ||
(!enc->enc_pic.rc_per_pic.qp_p && enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].quant_p_frames) ||
(enc->enc_pic.rc_per_pic.qp_i != pic->rc[0].quant_i_frames) ||
(enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].quant_p_frames) ||
(enc->enc_pic.rc_per_pic.max_au_size_i != pic->rc[0].max_au_size) ||
(enc->enc_pic.rc_per_pic.qvbr_quality_level != pic->rc[0].vbr_quality_factor);
} else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_AV1) {
struct pipe_av1_enc_picture_desc *pic = (struct pipe_av1_enc_picture_desc *)picture;
@ -1385,14 +1376,11 @@ static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
(enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rc[0].frame_rate_num) ||
(enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rc[0].frame_rate_den);
if (enc->need_rate_control) {
enc->enc_pic.rc_per_pic.qp_i = 0;
enc->enc_pic.rc_per_pic.qp_p = 0;
}
enc->need_rc_per_pic =
(!enc->enc_pic.rc_per_pic.qp_i && enc->enc_pic.rc_per_pic.qp_i != pic->rc[0].qp) ||
(!enc->enc_pic.rc_per_pic.qp_p && enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].qp_inter) ||
(enc->enc_pic.rc_per_pic.qp_i != pic->rc[0].qp) ||
(enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].qp_inter) ||
(enc->enc_pic.rc_per_pic.qp_p != pic->rc[0].qp_inter) ||
(enc->enc_pic.rc_per_pic.max_au_size_i != pic->rc[0].max_au_size) ||
(enc->enc_pic.rc_per_pic.qvbr_quality_level != pic->rc[0].vbr_quality_factor);
if (!enc->cdf) {