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freedreno: improve a6xx CP_SET_MARKER xml definition
Use real names for most of a6xx_marker enum, add USES_GMEM, remove overlapping bitfields. Note the actual "real names" start with PM4_RENDER_MODE_ instead of RM6_ This is a small change to adreno_pm4.xml, with the corresponding find/replace and updated ci references Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30544>
This commit is contained in:
Jonathan Marek
Marge Bot
parent
022fb8e4c7
commit
72900e1aac
12 changed files with 4956 additions and 4953 deletions
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@ -1690,7 +1690,7 @@ got cmdszdw=27
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0000000000000000: 0000: 70460001 00000019
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opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_BYPASS | MARKER = RM6_BYPASS }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_DIRECT_RENDER }
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0000000100000000: 0000: 70e50001 00000001
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opcode: CP_NOP (10) (1 dwords)
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0000000100000008: 0000: 70108000
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File diff suppressed because it is too large
Load diff
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@ -399,10 +399,10 @@ cmdstream[0]: 265 dwords
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RB_BIN_CONTROL2: { BINW = 256 | BINH = 256 }
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0000000001058350: 0000: 4088d301 00001008
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_END }
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0000000001058358: 0000: 70e50001 00000007
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_GMEM | MARKER = RM6_GMEM }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_START }
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0000000001058360: 0000: 70e50001 00000004
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write GRAS_SC_WINDOW_SCISSOR_TL (80f0)
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GRAS_SC_WINDOW_SCISSOR_TL: { X = 0 | Y = 0 }
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@ -463,7 +463,7 @@ cmdstream[0]: 265 dwords
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opcode: CP_EVENT_WRITE (46) (2 dwords)
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{ EVENT = BLIT }
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event BLIT
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mode: RM6_GMEM
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mode: RM6_BIN_RENDER_START
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skip_ib2: g=0, l=0
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draw[1] register values
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!+ 06001008 GRAS_BIN_CONTROL: { BINW = 256 | BINH = 256 | RENDER_MODE = RENDERING_PASS | BUFFERS_LOCATION = BUFFERS_IN_GMEM | LRZ_FEEDBACK_ZMODE_MASK = 0x6 }
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@ -1276,7 +1276,7 @@ cmdstream[0]: 265 dwords
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{ INDIRECT = 0x1162008 }
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{ INDIRECT_COUNT = 0x116300c }
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{ STRIDE = 40 }
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mode: RM6_GMEM
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mode: RM6_BIN_RENDER_START
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skip_ib2: g=0, l=0
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indirect count: 2
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draw 0:
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@ -1517,7 +1517,7 @@ cmdstream[0]: 265 dwords
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opcode: CP_SKIP_IB2_ENABLE_GLOBAL (1d) (2 dwords)
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000000000115c010: 0000: 709d0001 00000000
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_RESOLVE | MARKER = RM6_RESOLVE }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RESOLVE }
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000000000115c018: 0000: 70e50001 00000006
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write RB_BLIT_SCISSOR_TL (88d1)
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RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
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@ -1544,7 +1544,7 @@ cmdstream[0]: 265 dwords
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opcode: CP_EVENT_WRITE (46) (2 dwords)
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{ EVENT = BLIT }
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event BLIT
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mode: RM6_RESOLVE
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mode: RM6_BIN_RESOLVE
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skip_ib2: g=0, l=0
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draw[3] register values
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+ 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
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@ -342,7 +342,7 @@ cmdstream[0]: 1023 dwords
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:0,0,0,9
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0000000001d9139c: 0000: 48088a01 00000009
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_BINNING | MARKER = RM6_BINNING }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_VISIBILITY }
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0000000001d913a4: 0000: 70e50001 00000002
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d913ac: 0000: 70268000
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@ -856,7 +856,7 @@ cmdstream[0]: 1023 dwords
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{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
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{ NUM_INSTANCES = 1 }
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{ NUM_INDICES = 4 }
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mode: RM6_BINNING
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mode: RM6_BIN_VISIBILITY
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skip_ib2: g=0, l=0
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draw[0] register values
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!+ 00000001 CP_SCRATCH[0x5].REG: 1
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@ -1536,7 +1536,7 @@ cmdstream[0]: 1023 dwords
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:0,1,12,13
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0000000001d91998: 0000: 48088a01 0000000d
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x14 | MARKER = RM6_GMEM }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_START | USES_GMEM }
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0000000001d919a0: 0000: 70e50001 00000014
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d919a8: 0000: 70268000
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@ -1648,7 +1648,7 @@ cmdstream[0]: 1023 dwords
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opcode: CP_EVENT_WRITE (46) (2 dwords)
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{ EVENT = BLIT }
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event BLIT
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mode: RM6_GMEM
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mode: RM6_BIN_RENDER_START
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skip_ib2: g=1, l=0
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draw[1] register values
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+ 00000000 CP_SCRATCH[0].REG: 0
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@ -5142,7 +5142,7 @@ cmdstream[0]: 1023 dwords
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{ PRIM_TYPE = DI_PT_TRISTRIP | SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX | VIS_CULL = USE_VISIBILITY | INDEX_SIZE = INDEX4_SIZE_8_BIT | PATCH_TYPE = TESS_QUADS }
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{ NUM_INSTANCES = 1 }
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{ NUM_INDICES = 4 }
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mode: RM6_GMEM
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mode: RM6_BIN_RENDER_START
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skip_ib2: g=1, l=0
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draw[2] register values
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+ 00000001 CP_SCRATCH[0x5].REG: 1
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@ -6756,7 +6756,7 @@ cmdstream[0]: 1023 dwords
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{ DWORDS = 2 }
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0000000001d91ae4: 0000: 70c70002 10000000 00000002
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x15 | MARKER = RM6_ENDVIS }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_END_OF_DRAWS | USES_GMEM }
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0000000001d91af0: 0000: 70e50001 00000015
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opcode: CP_SET_DRAW_STATE (43) (4 dwords)
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{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
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@ -6772,7 +6772,7 @@ cmdstream[0]: 1023 dwords
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:0,1,18,19
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0000000001d91b14: 0000: 48088a01 00000013
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x16 | MARKER = RM6_RESOLVE }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RESOLVE | USES_GMEM }
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0000000001d91b1c: 0000: 70e50001 00000016
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91b24: 0000: 70268000
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@ -6814,7 +6814,7 @@ cmdstream[0]: 1023 dwords
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opcode: CP_EVENT_WRITE (46) (2 dwords)
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{ EVENT = BLIT }
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event BLIT
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mode: RM6_RESOLVE
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mode: RM6_BIN_RESOLVE
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skip_ib2: g=1, l=0
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draw[3] register values
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!+ 00000015 CP_SCRATCH[0x6].REG: 21
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@ -6844,7 +6844,7 @@ cmdstream[0]: 1023 dwords
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:0,1,22,8
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0000000001d91b50: 0000: 48088901 00000016
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_END }
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0000000001d91b58: 0000: 70e50001 00000007
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91b60: 0000: 70268000
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@ -6853,7 +6853,7 @@ cmdstream[0]: 1023 dwords
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:0,1,22,23
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0000000001d91b64: 0000: 48088a01 00000017
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x14 | MARKER = RM6_GMEM }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_START | USES_GMEM }
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0000000001d91b6c: 0000: 70e50001 00000014
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91b74: 0000: 70268000
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@ -6972,7 +6972,7 @@ cmdstream[0]: 1023 dwords
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{ DWORDS = 2 }
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0000000001d91cb0: 0000: 70c70002 10000000 00000002
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x15 | MARKER = RM6_ENDVIS }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_END_OF_DRAWS | USES_GMEM }
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0000000001d91cbc: 0000: 70e50001 00000015
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opcode: CP_SET_DRAW_STATE (43) (4 dwords)
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{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
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@ -6988,7 +6988,7 @@ cmdstream[0]: 1023 dwords
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:0,1,28,29
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0000000001d91ce0: 0000: 48088a01 0000001d
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x16 | MARKER = RM6_RESOLVE }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RESOLVE | USES_GMEM }
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0000000001d91ce8: 0000: 70e50001 00000016
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91cf0: 0000: 70268000
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@ -7013,7 +7013,7 @@ cmdstream[0]: 1023 dwords
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:0,1,32,30
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0000000001d91d1c: 0000: 48088901 00000020
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_END }
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0000000001d91d24: 0000: 70e50001 00000007
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91d2c: 0000: 70268000
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@ -7022,7 +7022,7 @@ cmdstream[0]: 1023 dwords
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:0,1,32,33
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0000000001d91d30: 0000: 48088a01 00000021
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x14 | MARKER = RM6_GMEM }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_START | USES_GMEM }
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0000000001d91d38: 0000: 70e50001 00000014
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91d40: 0000: 70268000
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@ -7141,7 +7141,7 @@ cmdstream[0]: 1023 dwords
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{ DWORDS = 2 }
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0000000001d91e7c: 0000: 70c70002 10000000 00000002
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x15 | MARKER = RM6_ENDVIS }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_END_OF_DRAWS | USES_GMEM }
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0000000001d91e88: 0000: 70e50001 00000015
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opcode: CP_SET_DRAW_STATE (43) (4 dwords)
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{ COUNT = 0 | DISABLE_ALL_GROUPS | GROUP_ID = 0 }
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@ -7157,7 +7157,7 @@ cmdstream[0]: 1023 dwords
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:0,1,38,39
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0000000001d91eac: 0000: 48088a01 00000027
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x16 | MARKER = RM6_RESOLVE }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RESOLVE | USES_GMEM }
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0000000001d91eb4: 0000: 70e50001 00000016
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91ebc: 0000: 70268000
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@ -7182,7 +7182,7 @@ cmdstream[0]: 1023 dwords
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:0,1,42,40
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0000000001d91ee8: 0000: 48088901 0000002a
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = RM6_YIELD | MARKER = RM6_YIELD }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_END }
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0000000001d91ef0: 0000: 70e50001 00000007
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91ef8: 0000: 70268000
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@ -7191,7 +7191,7 @@ cmdstream[0]: 1023 dwords
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:0,1,42,43
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0000000001d91efc: 0000: 48088a01 0000002b
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opcode: CP_SET_MARKER (65) (2 dwords)
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{ MODE = 0x14 | MARKER = RM6_GMEM }
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{ MARKER_MODE = SET_RENDER_MODE | MODE = RM6_BIN_RENDER_START | USES_GMEM }
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0000000001d91f04: 0000: 70e50001 00000014
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opcode: CP_WAIT_FOR_IDLE (26) (1 dwords)
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0000000001d91f0c: 0000: 70268000
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File diff suppressed because it is too large
Load diff
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@ -15,7 +15,7 @@ Blit:
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Batch:
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-------
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# of draws: 1
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mode: RM6_GMEM
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mode: RM6_BIN_RENDER_START
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bin size: 768x320 (35 bins)
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DEPTHTEST DEPTHWRITE
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MRT[0x4715000:0x0]: 3840x2160 FMT6_Z24_UNORM_S8_UINT (MSAA_ONE) CLEARED RESOLVED
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@ -35,7 +35,7 @@ Blit:
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Batch:
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-------
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# of draws: 2
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mode: RM6_GMEM
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mode: RM6_BIN_RENDER_START
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bin size: 640x192 (18 bins)
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DEPTHTEST DEPTHWRITE
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MRT[0x28fc000:0x0]: 1920x1080 FMT6_Z24_UNORM_S8_UINT (MSAA_ONE) CLEARED RESOLVED
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@ -2655,11 +2655,11 @@ cp_set_marker(uint32_t *dwords, uint32_t sizedwords, int level)
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render_mode = mode;
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if (!strcmp(render_mode, "RM6_BINNING")) {
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if (!strcmp(render_mode, "RM6_BIN_VISIBILITY")) {
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enable_mask = MODE_BINNING;
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} else if (!strcmp(render_mode, "RM6_GMEM")) {
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} else if (!strcmp(render_mode, "RM6_BIN_RENDER_START")) {
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enable_mask = MODE_GMEM;
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} else if (!strcmp(render_mode, "RM6_BYPASS")) {
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} else if (!strcmp(render_mode, "RM6_DIRECT_RENDER")) {
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enable_mask = MODE_BYPASS;
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}
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}
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@ -108,7 +108,7 @@ function finish()
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printf("-------\n")
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printf(" # of draws: %u\n", draws)
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printf(" mode: %s\n", drawmode)
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if drawmode == "RM6_GMEM" then
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if drawmode == "RM6_BIN_RENDER_START" then
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printf(" bin size: %ux%u (%u bins)\n", binw, binh, nbins)
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end
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if depthtest or depthwrite then
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@ -138,7 +138,7 @@ function finish()
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for base,mrt in pairs(mrts) do
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printf(" MRT[0x%x:0x%x]:\t%ux%u\t\t%s (%s)", base, mrt.flag, mrt.w, mrt.h, mrt.format, mrt.samples)
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if drawmode == "RM6_GMEM" then
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if drawmode == "RM6_BIN_RENDER_START" then
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if cleared[mrt.gmem] then
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printf("\tCLEARED")
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end
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@ -183,7 +183,7 @@ end
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-- Track the current mode:
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local mode = ""
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function CP_SET_MARKER(pkt, size)
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mode = pkt[0].MARKER
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mode = pkt[0].MODE
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dbg("mode: %s\n", mode)
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end
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@ -193,7 +193,7 @@ function CP_EVENT_WRITE(pkt, size)
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end
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nullbatch = false
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local m = tostring(mode)
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if m == "RM6_GMEM" then
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if m == "RM6_BIN_RENDER_START" then
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-- either clear or restore:
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if r.RB_BLIT_INFO.CLEAR_MASK == 0 then
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restored[r.RB_BLIT_BASE_GMEM] = 1
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@ -237,7 +237,7 @@ function CP_EVENT_WRITE(pkt, size)
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sysmem,
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flag,
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r.RB_BLIT_BASE_GMEM)
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elseif m == "RM6_RESOLVE" then
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elseif m == "RM6_BIN_RESOLVE" then
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resolved[r.RB_BLIT_BASE_GMEM] = 1
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else
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printf("I am confused!!!\n")
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@ -291,10 +291,10 @@ function handle_blit()
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end
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function valid_transition(curmode, newmode)
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if curmode == "RM6_BINNING" and newmode == "RM6_GMEM" then
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if curmode == "RM6_BIN_VISIBILITY" and newmode == "RM6_BIN_RENDER_START" then
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return true
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end
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if curmode == "RM6_GMEM" and newmode == "RM6_RESOLVE" then
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if curmode == "RM6_BIN_RENDER_START" and newmode == "RM6_BIN_RESOLVE" then
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return true
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end
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return false
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@ -324,12 +324,12 @@ function draw(primtype, nindx)
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end
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end
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if m ~= "RM6_GMEM" and m ~= "RM6_BYPASS" then
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if m == "RM6_BINNING" then
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if m ~= "RM6_BIN_RENDER_START" and m ~= "RM6_DIRECT_RENDER" then
|
||||
if m == "RM6_BIN_VISIBILITY" then
|
||||
drawmode = m
|
||||
return
|
||||
end
|
||||
if m == "RM6_RESOLVE" and primtype == "EVENT:BLIT" then
|
||||
if m == "RM6_BIN_RESOLVE" and primtype == "EVENT:BLIT" then
|
||||
return
|
||||
end
|
||||
if m == "RM6_BLIT2DSCALE" and primtype == "EVENT:LRZ_CLEAR" then
|
||||
|
|
@ -341,7 +341,7 @@ function draw(primtype, nindx)
|
|||
|
||||
-- Only count the first tile for GMEM mode to avoid counting
|
||||
-- each draw for each tile
|
||||
if m == "RM6_GMEM" then
|
||||
if m == "RM6_BIN_RENDER_START" then
|
||||
if r.RB_WINDOW_OFFSET.X ~= 0 or r.RB_WINDOW_OFFSET.Y ~= 0 then
|
||||
return
|
||||
end
|
||||
|
|
@ -400,7 +400,7 @@ function draw(primtype, nindx)
|
|||
|
||||
-- TODO should also check for stencil buffer for z32+s8 case
|
||||
|
||||
if m == "RM6_GMEM" then
|
||||
if m == "RM6_BIN_RENDER_START" then
|
||||
binw = r.VSC_BIN_SIZE.WIDTH
|
||||
binh = r.VSC_BIN_SIZE.HEIGHT
|
||||
nbins = r.VSC_BIN_COUNT.NX * r.VSC_BIN_COUNT.NY
|
||||
|
|
|
|||
|
|
@ -3873,8 +3873,8 @@ to upconvert to 32b float internally?
|
|||
<!-- set when this is the last resolve on a650+ -->
|
||||
<bitfield name="LAST" low="8" high="9"/>
|
||||
<!--
|
||||
a618 GLES: color render target number being resolved for RM6_RESOLVE, 0x8 for depth, 0x9 for separate stencil.
|
||||
a618 VK: 0x8 for depth RM6_RESOLVE, 0x9 for separate stencil, 0 otherwise.
|
||||
a618 GLES: color render target number being resolved for CCU_RESOLVE, 0x8 for depth, 0x9 for separate stencil.
|
||||
a618 VK: 0x8 for depth CCU_RESOLVE, 0x9 for separate stencil, 0 otherwise.
|
||||
|
||||
We believe this is related to concurrent resolves
|
||||
-->
|
||||
|
|
|
|||
|
|
@ -1779,13 +1779,23 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
|
||||
<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
|
||||
<doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
|
||||
<enum name="set_marker_mode">
|
||||
<value value="0" name="SET_RENDER_MODE"/>
|
||||
<!-- IFPC - inter-frame power collapse -->
|
||||
<value value="1" name="SET_IFPC_MODE"/>
|
||||
</enum>
|
||||
<enum name="a6xx_ifpc_mode">
|
||||
<value value="0" name="IFPC_ENABLE"/>
|
||||
<value value="1" name="IFPC_DISABLE"/>
|
||||
</enum>
|
||||
<enum name="a6xx_marker">
|
||||
<value value="1" name="RM6_BYPASS"/>
|
||||
<value value="2" name="RM6_BINNING"/>
|
||||
<value value="4" name="RM6_GMEM"/>
|
||||
<value value="5" name="RM6_ENDVIS"/>
|
||||
<value value="6" name="RM6_RESOLVE"/>
|
||||
<value value="7" name="RM6_YIELD"/>
|
||||
<value value="1" name="RM6_DIRECT_RENDER"/>
|
||||
<value value="2" name="RM6_BIN_VISIBILITY"/>
|
||||
<value value="3" name="RM6_BIN_DIRECT"/>
|
||||
<value value="4" name="RM6_BIN_RENDER_START"/>
|
||||
<value value="5" name="RM6_BIN_END_OF_DRAWS"/>
|
||||
<value value="6" name="RM6_BIN_RESOLVE"/>
|
||||
<value value="7" name="RM6_BIN_RENDER_END"/>
|
||||
<value value="8" name="RM6_COMPUTE"/>
|
||||
<value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
|
||||
|
||||
|
|
@ -1795,23 +1805,16 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
-->
|
||||
<value value="0xd" name="RM6_IB1LIST_START"/>
|
||||
<value value="0xe" name="RM6_IB1LIST_END"/>
|
||||
<!-- IFPC - inter-frame power collapse -->
|
||||
<value value="0x100" name="RM6_IFPC_ENABLE"/>
|
||||
<value value="0x101" name="RM6_IFPC_DISABLE"/>
|
||||
</enum>
|
||||
<reg32 offset="0" name="0">
|
||||
<!--
|
||||
NOTE: blob driver and some versions of freedreno/turnip set
|
||||
b4, which is unused (at least by current sqe fw), but interferes
|
||||
with parsing if we extend the size of the bitfield to include
|
||||
b8 (only sent by kernel mode driver). Really, the way the
|
||||
parsing works in the firmware, only b0-b3 are considered, but
|
||||
if b8 is set, the low bits are interpreted differently. To
|
||||
model this, without getting confused by spurious b4, this is
|
||||
described as two overlapping bitfields:
|
||||
-->
|
||||
<bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
|
||||
<bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
|
||||
<!-- if b8 is set, the low bits are interpreted differently (and b4 ignored) -->
|
||||
<bitfield name="MARKER_MODE" pos="8" type="set_marker_mode" addvariant="yes"/>
|
||||
|
||||
<bitfield name="MODE" low="0" high="3" type="a6xx_marker" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
<!-- used by preemption to determine if GMEM needs to be saved or not -->
|
||||
<bitfield name="USES_GMEM" pos="4" type="boolean" varset="set_marker_mode" variants="SET_RENDER_MODE"/>
|
||||
|
||||
<bitfield name="IFPC_MODE" pos="0" type="a6xx_ifpc_mode" varset="set_marker_mode" variants="SET_IFPC_MODE"/>
|
||||
</reg32>
|
||||
</domain>
|
||||
|
||||
|
|
@ -1941,11 +1944,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
a bitmask of which modes pass the test.
|
||||
-->
|
||||
|
||||
<!-- RM6_BINNING -->
|
||||
<!-- RM6_BIN_VISIBILITY -->
|
||||
<bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
|
||||
<!-- all others -->
|
||||
<bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
|
||||
<!-- RM6_BYPASS -->
|
||||
<!-- RM6_DIRECT_RENDER -->
|
||||
<bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
|
||||
|
||||
<bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
|
||||
|
|
@ -2032,7 +2035,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
|
|||
<doc>
|
||||
Executed when switching back after switching
|
||||
away during execution of
|
||||
a CP_SET_MARKER packet with RM6_YIELD as the
|
||||
a CP_SET_MARKER packet with RM6_BIN_RENDER_END as the
|
||||
payload *and* skipsaverestore is set. This is
|
||||
expected to restore static register values not
|
||||
saved when skipsaverestore is set.
|
||||
|
|
|
|||
|
|
@ -1003,7 +1003,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
|
|||
const struct tu_tiling_config *tiling = cmd->state.tiling;
|
||||
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START));
|
||||
|
||||
const uint32_t x1 = tiling->tile0.width * tx;
|
||||
const uint32_t y1 = tiling->tile0.height * ty;
|
||||
|
|
@ -1197,7 +1197,7 @@ tu6_emit_tile_store(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
|
|||
tu_cs_set_writeable(cs, true);
|
||||
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RESOLVE));
|
||||
|
||||
tu6_emit_blit_scissor(cmd, cs, true);
|
||||
|
||||
|
|
@ -1560,7 +1560,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
|
|||
tu6_emit_window_scissor(cs, 0, 0, fb->width - 1, fb->height - 1);
|
||||
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_VISIBILITY));
|
||||
|
||||
tu_cs_emit_pkt7(cs, CP_SET_VISIBILITY_OVERRIDE, 1);
|
||||
tu_cs_emit(cs, 0x1);
|
||||
|
|
@ -1933,7 +1933,7 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
|
|||
}
|
||||
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER));
|
||||
|
||||
/* A7XX TODO: blob doesn't use CP_SKIP_IB2_ENABLE_* */
|
||||
tu_cs_emit_pkt7(cs, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
|
||||
|
|
@ -2100,7 +2100,7 @@ tu6_render_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
|
|||
|
||||
if (use_hw_binning(cmd)) {
|
||||
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
|
||||
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_END_OF_DRAWS));
|
||||
}
|
||||
|
||||
/* Predicate is changed in draw_cs so we have to re-emit it */
|
||||
|
|
|
|||
|
|
@ -943,7 +943,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
|
|||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_VISIBILITY));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
|
||||
|
|
@ -1192,7 +1192,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
|
|||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RENDER_START));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
uint32_t x1 = tile->xoff;
|
||||
|
|
@ -1774,7 +1774,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
|
|||
|
||||
if (use_hw_binning(batch)) {
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_END_OF_DRAWS));
|
||||
}
|
||||
|
||||
OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
|
||||
|
|
@ -1789,7 +1789,7 @@ fd6_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
|
|||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BIN_RESOLVE));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
if (batch->tile_store) {
|
||||
|
|
@ -1931,7 +1931,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
|
|||
|
||||
emit_marker6(ring, 7);
|
||||
OUT_PKT7(ring, CP_SET_MARKER, 1);
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS));
|
||||
OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_DIRECT_RENDER));
|
||||
emit_marker6(ring, 7);
|
||||
|
||||
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue