Commit graph

218095 commits

Author SHA1 Message Date
Marek Olšák
6f36a2be2e ac: unify HTILE codes and encoding
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39631>
2026-02-03 17:10:32 +00:00
Marek Olšák
e0c7c642f4 ac: unify and demystify CMASK clear codes
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39631>
2026-02-03 17:10:32 +00:00
Marek Olšák
43e9af713b radv: use DCC definitions more
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39631>
2026-02-03 17:10:31 +00:00
Marek Olšák
6af6197136 ac: unify DCC clear code definitions
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39631>
2026-02-03 17:10:30 +00:00
Juan A. Suarez Romero
7bc1736006 broadcom/cle: ensure zlib inflate assign memory
This basic assertion helps static analyzer to avoid complaining that the
data memory could be NULL when we copy data from there later.

This fixes static analyzer warning null pointer passed to 2nd parameter expecting 'nonnull'

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39577>
2026-02-03 16:44:13 +00:00
Juan A. Suarez Romero
5a85b3d9f4 broadcom/cle: bump up gen version for v3d
The generation version for V3D XML package was marked as 3.3, but
actually we removed all the code supporting this generation, and the
generations we support now are from 4.2 onwards.

So we bump up the generation version.

Fixes: 9c4829473a ("broadcom/cle: remove v33 and v41 from xml definition")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39577>
2026-02-03 16:44:13 +00:00
Dhruv Mark Collins
e8fc50ef46 freedreno,u_trace: Fix various UBSAN errors
These are a handful of errors that pop up in UBSAN, a lot of them
depend on compiler-specific behavior such as zero-sized VLAs being
valid, while others plugged some potential bug prone code such as
nullptr derefs.

Signed-off-by: Dhruv Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39662>
2026-02-03 16:14:35 +00:00
Loïc Molinari
ae41474d8c panfrost: Add new CPU scope traces
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
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New traces can safely be added now that they are disabled by default.

Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39407>
2026-02-03 15:41:51 +00:00
Loïc Molinari
cc933d1d08 panfrost: Port CPU scope traces to PAN_TRACE_*()
Use the new Mesa CPU trace wrappers to give Panfrost traces a
category. For builds with either Perfetto, Gpuvis or sysprof enabled,
Panfrost traces must now be enabled at run-time through the PAN_TRACE
environment variable. It removes the CPU cost of traces when traces
aren't used, it allows users to enable traces based on the needed
categories and it will allow to add new traces without worrying about
the CPU cost.

Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39407>
2026-02-03 15:41:51 +00:00
Loïc Molinari
1bca181580 pan/trace: Add wrappers for Mesa CPU scope traces
Add the PAN_TRACE_SCOPE() and PAN_TRACE_FUNC() wrappers based on
MESA_TRACE_SCOPE_IF() in order to associate a category to each trace
and let users select the set of tracing categories to enable at
run-time through the PAN_CPU_TRACE environment variable. This makes
Panfrost tracing an opt-in and avoids to CPU cost of tracing by
default.

There are 3 categories for now:
  - "lib" for the shared utilities
  - "gl" for the Gallium driver
  - "vk" for the Vulkan driver

Each of these categories are divided into subcategories so that
subsystems can easily be traced ("gl.csf" or "lib.kmod" for instance).

Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39407>
2026-02-03 15:41:50 +00:00
Loïc Molinari
c9097e2e13 util/perf: Add support for conditional CPU scope traces
Add a 'cond' argument to the _MESA_TRACE_SCOPE(),
_MESA_TRACE_SCOPE_NAME() and _MESA_TRACE_SCOPE_FLOW() macros, fix up
the MESA_TRACE_SCOPE(), MESA_TRACE_SCOPE_FLOW(), MESA_TRACE_FUNC() and
MESA_TRACE_FUNC_FLOW() macros depending on it and add the new
MESA_TRACE_SCOPE_IF(), MESA_TRACE_SCOPE_FLOW_IF(),
MESA_TRACE_FUNC_IF() and MESA_TRACE_FUNC_FLOW_IF() conditional macros.

The trace macros are now based on the conditional ones. Code gen stays
the same for all the current traces though since compilers optimize
out the condition to always taken. See the compiler explorer link.

Conditional CPU scope traces are meant to allow builds with either
Perfetto, Gpuvis or sysprof tracing enabled to filter traces at
run-time.

Link: https://godbolt.org/z/886PKWEqf
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39407>
2026-02-03 15:41:50 +00:00
Loïc Molinari
a336e9330d util/perf: Reorder ending CPU scope traces to match beginning order
Reorder trace calls in _mesa_trace_scope_end() to match the order in
the _mesa_trace_scope_*begin*() functions: Perfetto, Gpuvis then
Sysprof.

Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39407>
2026-02-03 15:41:50 +00:00
Loïc Molinari
b9cdefd406 util/perf: Replace tabs with spaces
Signed-off-by: Loïc Molinari <loic.molinari@collabora.com>
Reviewed-by: Ashley Smith <ashley.smith@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39407>
2026-02-03 15:41:50 +00:00
Utku Iseri
312372250a zink: add arrayness I/O matching
When an XFB-enabled pre-raster stage is combined with a fragment
shader that addresses the array that contains the XFB variables
indirectly, there's a mismatch of arrayness that occurs between
these two stages.

Overcome this hurdle by lowering the indirectly addressed FS
array to be directly accessed through a local copy of the array.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37602>
2026-02-03 15:21:49 +00:00
Christoph Pillmayer
b526b971f1 pan/bi: Make SSA spilling vector aware
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
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For example, when we spill a COLLECT, the single SSA result
represents more than just one HW register / more than 32bits.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:16 +00:00
Christoph Pillmayer
2fd5b8a391 pan/bi: Account for MEMMOV in bi_record_sizes
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:16 +00:00
Christoph Pillmayer
0654c98b5e pan/bi: Don't allocate lut space for temps
Since we now reserve space for memory variables, the indices for
the potential temporaries would now start at 2*ctx->ssa_alloc.

We only create temps in insert_coupling_code and none of those are
used in functions that look up things in the various luts. Only
where the temps are created we have to take care to not pass those
into bi_index_as_memory.

Therefore, let's not allocate any space for them. Otherwise we
would have to double the size of the luts to account for the
memory variables.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:16 +00:00
Christoph Pillmayer
79c786ea6e pan/bi: Abstract away spills/fills when spilling
We want to lower spills and fills to actual LS instructions only
after SSA register allocation which future commits will add.
For now, we just lower the new MEMMOV instr immediately.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:15 +00:00
Christoph Pillmayer
0e55a87901 pan/bi: Pull out size recording
We need this again afterwards to record sizes again after
repairing ssa form.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:15 +00:00
Christoph Pillmayer
4bbd314580 pan/bi: Teach bi_print_instr about memory vars
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:15 +00:00
Christoph Pillmayer
4fba6b984f pan/bi: Repair SSA after spilling
In order to implement SSA based register allocation, we need to
restore the SSA form after spilling.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:14 +00:00
Christoph Pillmayer
dd94d1833f pan/bi: Fixup bi_repair_ssa.c for bi
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:14 +00:00
Christoph Pillmayer
f29fa1e9df pan/bi: Fixup bi_reindex_ssa.c for bi
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:13 +00:00
Christoph Pillmayer
63a8232c1a pan/bi: Copy reindex_ssa.c from agx
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:13 +00:00
Christoph Pillmayer
2c6f17d517 pan/bi: Copy agx_repair_ssa.c
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:13 +00:00
Christoph Pillmayer
62925ea831 pan/bi: Reindex SSA before NIR->BIR
Otherwise we potentially waste space in the various lookup tables.

Happens for example in:
dEQP-VK.spirv_assembly.instruction.graphics.composite_insert.nested_struct_frag

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:13 +00:00
Christoph Pillmayer
1a9fd2b10e pan/bi: Fix spill limit value order
When the register pressure is at the allowed maximum and we have
instructions like the following, preferring rematerializable values
in cmp_dist means that we evict the source of an instruction before
it is even used. This makes no sense.

10 = LOAD_CONST
11 = LOAD_CONST     // here we would evict 10!
12 = USE 10!, 11!

Happens in dEQP-VK.spirv_assembly.instruction.compute.opphi.wide
at the beginning of block1.

Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:13 +00:00
Christoph Pillmayer
6b81eb58f3 pan: Add some missing ForEachMacros to .clang-format
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39305>
2026-02-03 13:26:12 +00:00
Maaz Mombasawala
bea618b4de svga: Update CI expectations
Some checks are pending
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Marking test as failure as seen in job -
https://gitlab.freedesktop.org/mombasa/mesa/-/jobs/92373639
so that we can enable vmware ci farm.

Signed-off-by: Maaz Mombasawala <maaz.mombasawala@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39665>
2026-02-03 08:33:33 +00:00
Qiang Yu
f20cd07e21 radeonsi: fix mesh shader outputs kill
Mesh shader uses store per vertex output for point size
and store per primitive output for layer id.

This fixes gpu-ratemeter run slow for kill point size
and layer id cases when mono shader is used which expect
to kill these outputs.

Also gather fragment shader per primitive input info
to kill mesh shader per primitive output.

Fixes: e6e21dfbf2 ("radeonsi: kill outputs for mesh shader")
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39644>
2026-02-03 07:52:07 +00:00
Qiang Yu
5b159025d7 radeonsi: not overlap ib print for multi context
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39644>
2026-02-03 07:52:07 +00:00
Qiang Yu
a0678f3c00 radeonsi: be able to record sqtt for frame 0|1 and no swap
It was not possible to enable sqtt for first and second
frame because AMD_THREAD_TRACE_TRIGGER must be positive
and we missed call si_handle_sqtt at the beginning of
the first frame.

To support some test which does not swap buffer, add a
call to si_handle_sqtt when destroy context.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39644>
2026-02-03 07:52:07 +00:00
Qiang Yu
3aea4691bb radeonsi: mesh shader support sqtt
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39644>
2026-02-03 07:52:07 +00:00
Qiang Yu
1ca7d564b6 radeonsi: move sqtt draw code to shared function with mesh pipeline
No function change.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39644>
2026-02-03 07:52:07 +00:00
Kenneth Graunke
6ea4fe9806 iris: Switch to SPDX headers
Some checks are pending
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39663>
2026-02-03 01:30:41 +00:00
Valentine Burley
0f3b51a165 ci/deqp: Retry GitHub API lookup for main-branch check
Some checks are pending
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The GitHub compare API used to verify that DEQP_MAIN_COMMIT is based
on main is very fragile, causing many container build failures.

Add simple retry logic to make the check more robust.

Signed-off-by: Valentine Burley <valentine.burley@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39649>
2026-02-03 00:01:22 +00:00
Alyssa Rosenzweig
bc69e4364f intel: report code size in shader stats
This is missing from ANV's statistics currently.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39633>
2026-02-02 23:30:24 +00:00
Alyssa Rosenzweig
fc53da9c39 intel: simplify shader stats names
This brings what ANV reports closer to what Iris reports, and is mostly dropping
redundancies.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39633>
2026-02-02 23:30:24 +00:00
Alyssa Rosenzweig
3d5170c705 intel: add scheduling mode statistic
This is for parity with what we do in the current GL shader-db path.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39633>
2026-02-02 23:30:24 +00:00
Alyssa Rosenzweig
fcaf6a52a7 util: hide hashes from GL shader stats
Traditionally we don't print these for GL and tooling doesn't know about this.
Just drop them. Note that neither AMD nor Intel uses the common GL print path
yet which is why this hadn't been hit.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39633>
2026-02-02 23:30:24 +00:00
Alyssa Rosenzweig
0718a2e74c util: allow string shader "statistics"
This is useful for Intel reporting scheduling strategy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39633>
2026-02-02 23:30:24 +00:00
Alyssa Rosenzweig
3b20cfc589 pvr,pan,agx: drop cargo-culted nir_opt_loop calls
The comment claims this was to unroll loops, but nir_opt_loop doesn't do that.
Whatever issue the AGX code was originally working around, it doesn't apply now
(I confirmed we produce similar code with or without the pass). In the meantime,
Panfrost and PowerVR cargo-culted the same broken logic. Drop it all.

Closes: #14732
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39588>
2026-02-02 23:16:22 +00:00
Ian Forbes
27474b2ce3 svga: Always emit VGPU10_OPCODE_DCL_GLOBAL_FLAGS for VGPU10
The NOP that sometimes gets emitted when no flags are set was causing
problems with the TC shader declarations on the device side causing the
arb_tesselation_shader@execution@built-in-functions piglit test to fail.

We can always emit the declaration and leave the flags as zero if they
are not enabled rather than outputting the problematic NOP.

Signed-off-by: Ian Forbes <ian.forbes@broadcom.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39660>
2026-02-02 22:59:34 +00:00
Marek Olšák
a3f022d0a2 nir: reassociate a $op (b ? #c : #d) for div, mod, rem
Some checks are pending
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This eliminates expensive div, mod, rem opcodes with non-constant src1 being
constant src1 hiding behind bcsel.

gcc and LLVM are missing this.

Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39560>
2026-02-02 21:34:48 +00:00
Marek Olšák
ee16f76a1e radeonsi: don't allocate a VB descriptor upload buffer if it's not needed
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39536>
2026-02-02 21:09:46 +00:00
Marek Olšák
bdb36e5be5 radeonsi: move VB descriptor emission and upload into separate functions
This reduces duplication by putting the IS_DRAW_VERTEX_STATE constant
inside the loops.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39536>
2026-02-02 21:09:46 +00:00
Marek Olšák
f096652aec ac/llvm: pass soffset to buffer_load/store_format
this will be needed in the future

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39536>
2026-02-02 21:09:46 +00:00
Marek Olšák
d6a5bb3808 ac/llvm: simplify emitting FP intrinsics
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39536>
2026-02-02 21:09:46 +00:00
Marek Olšák
74bc4ee9f3 ac/llvm: remove scalarizing emit_intrin_1f_param_scalar
we scalarize this in NIR

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39536>
2026-02-02 21:09:45 +00:00
Tapani Pälli
6979f9f0d5 anv: use workaround framework for Wa_1508208842
Some checks are pending
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Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39622>
2026-02-02 19:40:26 +00:00