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radeonsi: move sqtt draw code to shared function with mesh pipeline
No function change. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39644>
This commit is contained in:
Qiang Yu
Marge Bot
parent
6ea4fe9806
commit
1ca7d564b6
1 changed files with 105 additions and 105 deletions
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@ -269,6 +269,111 @@ static bool si_update_shaders_shared_by_vertex_and_mesh_pipe(struct si_context *
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}
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}
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if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt)) {
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/* Pretend the bound shaders form a vk pipeline. Include the scratch size in
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* the hash calculation to force re-emitting the pipeline if the scratch bo
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* changes.
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*/
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uint64_t scratch_bo_size = sctx->scratch_buffer ? sctx->scratch_buffer->bo_size : 0;
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uint32_t total_size = 0;
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/* Compute pipeline code hash. */
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XXH64_state_t* xh = XXH64_createState();
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XXH64_reset(xh, scratch_bo_size);
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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/* Hash the key. */
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XXH64_update(xh, &shader->key, sizeof(shader->key));
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/* Hash the main part binary. */
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XXH64_update(xh, shader->binary.code_buffer, shader->binary.code_size);
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total_size += (uint32_t)align_uintptr(shader->binary.uploaded_code_size, 256);
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}
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}
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XXH64_hash_t pipeline_code_hash = XXH64_digest(xh);
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XXH64_freeState(xh);
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struct si_sqtt_fake_pipeline *pipeline = NULL;
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if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
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/* This is a new pipeline. Allocate a new bo to hold all the shaders. Without
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* this, shader code export process creates huge rgp files because RGP assumes
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* the shaders live sequentially in memory (shader N address = shader 0 + offset N)
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*/
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struct si_resource *bo = si_aligned_buffer_create(
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&sctx->screen->b,
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SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT,
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PIPE_USAGE_IMMUTABLE, align(total_size, SI_CPDMA_ALIGNMENT), 256);
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char *ptr = (char *) (bo ? sctx->screen->ws->buffer_map(sctx->screen->ws,
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bo->buf, NULL,
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(enum pipe_map_flags)(PIPE_MAP_READ_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY)) :
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NULL);
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uint32_t offset = 0;
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uint64_t scratch_va = sctx->scratch_buffer ? sctx->scratch_buffer->gpu_address : 0;
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if (ptr) {
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pipeline = (struct si_sqtt_fake_pipeline *)
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CALLOC(1, sizeof(struct si_sqtt_fake_pipeline));
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pipeline->code_hash = pipeline_code_hash;
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pipeline->bo = bo;
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/* Re-upload all gfx shaders and init PM4. */
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si_pm4_clear_state(&pipeline->pm4, sctx->screen, false);
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uint32_t gfx_sh_offsets[SI_NUM_GRAPHICS_SHADERS] = { 0 };
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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struct si_resource *original_bo = shader->bo;
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/* Temp override for si_shader_binary_upload_at to work. */
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shader->bo = pipeline->bo;
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int size = si_shader_binary_upload_at(sctx->screen, shader, scratch_va, offset);
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shader->bo = original_bo;
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assert(size == (int)shader->binary.uploaded_code_size);
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gfx_sh_offsets[i] = offset;
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offset += align(size, 256);
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struct si_pm4_state *pm4 = &shader->pm4;
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/* Patch the SPI_SHADER_PGM_LO_* register to point to the new bo address,
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* with the proper offset.
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*/
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uint64_t va_low = shader->gpu_address >> 8;
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uint32_t reg = pm4->base.spi_shader_pgm_lo_reg;
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ac_pm4_set_reg(&pipeline->pm4.base, reg, va_low);
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}
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}
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ac_pm4_finalize(&pipeline->pm4.base);
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sctx->screen->ws->buffer_unmap(sctx->screen->ws, bo->buf);
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_mesa_hash_table_u64_insert(sctx->sqtt->pipeline_bos,
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pipeline_code_hash, pipeline);
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si_sqtt_register_pipeline(sctx, pipeline, gfx_sh_offsets);
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} else {
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if (bo)
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si_resource_reference(&bo, NULL);
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}
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} else {
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pipeline = (struct si_sqtt_fake_pipeline *)_mesa_hash_table_u64_search(
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sctx->sqtt->pipeline_bos, pipeline_code_hash);
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}
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assert(pipeline);
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si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 0);
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si_pm4_bind_state(sctx, sqtt_pipeline, pipeline);
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}
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return true;
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}
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@ -444,111 +549,6 @@ static bool si_update_shaders(struct si_context *sctx)
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if (!si_update_shaders_shared_by_vertex_and_mesh_pipe<GFX_VERSION, HAS_TESS, HAS_GS, MS_OFF, NGG>(sctx, old_vs, hw_vs))
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return false;
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if (GFX_VERSION >= GFX9 && unlikely(sctx->sqtt)) {
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/* Pretend the bound shaders form a vk pipeline. Include the scratch size in
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* the hash calculation to force re-emitting the pipeline if the scratch bo
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* changes.
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*/
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uint64_t scratch_bo_size = sctx->scratch_buffer ? sctx->scratch_buffer->bo_size : 0;
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uint32_t total_size = 0;
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/* Compute pipeline code hash. */
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XXH64_state_t* xh = XXH64_createState();
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XXH64_reset(xh, scratch_bo_size);
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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/* Hash the key. */
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XXH64_update(xh, &shader->key, sizeof(shader->key));
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/* Hash the main part binary. */
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XXH64_update(xh, shader->binary.code_buffer, shader->binary.code_size);
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total_size += (uint32_t)align_uintptr(shader->binary.uploaded_code_size, 256);
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}
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}
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XXH64_hash_t pipeline_code_hash = XXH64_digest(xh);
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XXH64_freeState(xh);
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struct si_sqtt_fake_pipeline *pipeline = NULL;
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if (!si_sqtt_pipeline_is_registered(sctx->sqtt, pipeline_code_hash)) {
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/* This is a new pipeline. Allocate a new bo to hold all the shaders. Without
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* this, shader code export process creates huge rgp files because RGP assumes
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* the shaders live sequentially in memory (shader N address = shader 0 + offset N)
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*/
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struct si_resource *bo = si_aligned_buffer_create(
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&sctx->screen->b,
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SI_RESOURCE_FLAG_DRIVER_INTERNAL | SI_RESOURCE_FLAG_32BIT,
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PIPE_USAGE_IMMUTABLE, align(total_size, SI_CPDMA_ALIGNMENT), 256);
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char *ptr = (char *) (bo ? sctx->screen->ws->buffer_map(sctx->screen->ws,
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bo->buf, NULL,
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(enum pipe_map_flags)(PIPE_MAP_READ_WRITE | PIPE_MAP_UNSYNCHRONIZED | RADEON_MAP_TEMPORARY)) :
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NULL);
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uint32_t offset = 0;
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uint64_t scratch_va = sctx->scratch_buffer ? sctx->scratch_buffer->gpu_address : 0;
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if (ptr) {
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pipeline = (struct si_sqtt_fake_pipeline *)
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CALLOC(1, sizeof(struct si_sqtt_fake_pipeline));
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pipeline->code_hash = pipeline_code_hash;
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pipeline->bo = bo;
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/* Re-upload all gfx shaders and init PM4. */
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si_pm4_clear_state(&pipeline->pm4, sctx->screen, false);
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uint32_t gfx_sh_offsets[SI_NUM_GRAPHICS_SHADERS] = { 0 };
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for (int i = 0; i < SI_NUM_GRAPHICS_SHADERS; i++) {
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struct si_shader *shader = sctx->shaders[i].current;
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if (sctx->shaders[i].cso && shader) {
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struct si_resource *original_bo = shader->bo;
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/* Temp override for si_shader_binary_upload_at to work. */
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shader->bo = pipeline->bo;
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int size = si_shader_binary_upload_at(sctx->screen, shader, scratch_va, offset);
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shader->bo = original_bo;
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assert(size == (int)shader->binary.uploaded_code_size);
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gfx_sh_offsets[i] = offset;
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offset += align(size, 256);
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struct si_pm4_state *pm4 = &shader->pm4;
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/* Patch the SPI_SHADER_PGM_LO_* register to point to the new bo address,
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* with the proper offset.
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*/
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uint64_t va_low = shader->gpu_address >> 8;
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uint32_t reg = pm4->base.spi_shader_pgm_lo_reg;
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ac_pm4_set_reg(&pipeline->pm4.base, reg, va_low);
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}
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}
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ac_pm4_finalize(&pipeline->pm4.base);
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sctx->screen->ws->buffer_unmap(sctx->screen->ws, bo->buf);
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_mesa_hash_table_u64_insert(sctx->sqtt->pipeline_bos,
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pipeline_code_hash, pipeline);
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si_sqtt_register_pipeline(sctx, pipeline, gfx_sh_offsets);
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} else {
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if (bo)
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si_resource_reference(&bo, NULL);
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}
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} else {
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pipeline = (struct si_sqtt_fake_pipeline *)_mesa_hash_table_u64_search(
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sctx->sqtt->pipeline_bos, pipeline_code_hash);
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}
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assert(pipeline);
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si_sqtt_describe_pipeline_bind(sctx, pipeline_code_hash, 0);
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si_pm4_bind_state(sctx, sqtt_pipeline, pipeline);
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}
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/* si_shader_select_with_key can clear the ngg_culling in the shader key if the shader
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* compilation hasn't finished. Set it to the same value in si_context.
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*/
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