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radv: use DCC definitions more

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39631>
This commit is contained in:
Marek Olšák 2026-01-30 13:48:35 -05:00 • committed by Marge Bot
parent 6af6197136
commit 43e9af713b
5 changed files with 7 additions and 7 deletions
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2
src/amd/vulkan/meta/radv_meta_clear.c
View file

@ -1981,7 +1981,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
enum radv_cmd_flush_bits flush_bits = 0;
for (unsigned i = 0; i < range_count; i++) {
if (radv_dcc_enabled(image, ranges[i].baseMipLevel))
flush_bits |= radv_clear_dcc(cmd_buffer, image, &ranges[i], 0xffffffffu);
flush_bits |= radv_clear_dcc(cmd_buffer, image, &ranges[i], DCC_UNCOMPRESSED);
}
cmd_buffer->state.flush_bits |= flush_bits;
}

2
src/amd/vulkan/meta/radv_meta_fast_clear.c
View file

@ -576,7 +576,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, subresourceRange);
/* Initialize the DCC metadata as "fully expanded". */
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, 0xffffffff);
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, DCC_UNCOMPRESSED);
}
void

2
src/amd/vulkan/meta/radv_meta_resolve.c
View file

@ -279,7 +279,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv
.layerCount = 1,
};
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, 0xffffffff);
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, DCC_UNCOMPRESSED);
}
VkRect2D resolve_area = {

2
src/amd/vulkan/meta/radv_meta_resolve_cs.c
View file

@ -357,7 +357,7 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_
.layerCount = vk_image_subresource_layer_count(&dst_image->vk, &region->dstSubresource),
};
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, 0xffffffff);
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, DCC_UNCOMPRESSED);
}
}

6
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -14379,10 +14379,10 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
}
if (radv_dcc_enabled(image, range->baseMipLevel)) {
uint32_t value = 0xffffffffu; /* Fully expanded mode. */
uint32_t value = DCC_UNCOMPRESSED; /* Fully expanded mode. */
if (radv_layout_dcc_compressed(device, image, range->baseMipLevel, dst_layout, dst_queue_mask)) {
value = 0u;
value = DCC_CLEAR_0000;
}
flush_bits |= radv_init_dcc(cmd_buffer, image, range, value);
@ -14443,7 +14443,7 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra
if (radv_dcc_enabled(image, range->baseMipLevel)) {
if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu);
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, DCC_UNCOMPRESSED);
} else if (radv_layout_dcc_compressed(device, image, range->baseMipLevel, src_layout, src_queue_mask) &&
!radv_layout_dcc_compressed(device, image, range->baseMipLevel, dst_layout, dst_queue_mask)) {
needs_dcc_decompress = true;