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ac: unify DCC clear code definitions

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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39631>
This commit is contained in:
Marek Olšák 2026-01-30 13:06:05 -05:00 • committed by Marge Bot
parent 7bc1736006
commit 6af6197136
3 changed files with 46 additions and 60 deletions
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28
src/amd/common/ac_descriptors.h
View file

@ -17,6 +17,34 @@
extern "C" {
#endif
#define DCC_CODE(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x))
enum
{
/* DCC clear codes for all generations. */
DCC_CLEAR_0000 = DCC_CODE(0x00), /* all bits are 0 */
DCC_UNCOMPRESSED = DCC_CODE(0xFF),
/* DCC clear codes for GFX8-10. */
GFX8_DCC_CLEAR_0000 = DCC_CLEAR_0000,
GFX8_DCC_CLEAR_0001 = DCC_CODE(0x40),
GFX8_DCC_CLEAR_1110 = DCC_CODE(0x80),
GFX8_DCC_CLEAR_1111 = DCC_CODE(0xC0),
GFX8_DCC_CLEAR_REG = DCC_CODE(0x20),
GFX9_DCC_CLEAR_SINGLE = DCC_CODE(0x10),
/* DCC clear codes for GFX11. */
GFX11_DCC_CLEAR_SINGLE = DCC_CODE(0x01),
GFX11_DCC_CLEAR_0000 = DCC_CLEAR_0000, /* all bits are 0 */
GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */
GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */
GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */
/* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 */
GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08),
/* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 */
GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A),
};
unsigned
ac_map_swizzle(unsigned swizzle);

52
src/amd/vulkan/meta/radv_meta_clear.c
View file

@ -1209,27 +1209,11 @@ radv_clear_htile(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
return flush_bits;
}
enum {
RADV_DCC_CLEAR_0000 = 0x00000000U,
RADV_DCC_GFX8_CLEAR_0001 = 0x40404040U,
RADV_DCC_GFX8_CLEAR_1110 = 0x80808080U,
RADV_DCC_GFX8_CLEAR_1111 = 0xC0C0C0C0U,
RADV_DCC_GFX8_CLEAR_REG = 0x20202020U,
RADV_DCC_GFX9_CLEAR_SINGLE = 0x10101010U,
RADV_DCC_GFX11_CLEAR_SINGLE = 0x01010101U,
RADV_DCC_GFX11_CLEAR_0000 = 0x00000000U,
RADV_DCC_GFX11_CLEAR_1111_UNORM = 0x02020202U,
RADV_DCC_GFX11_CLEAR_1111_FP16 = 0x04040404U,
RADV_DCC_GFX11_CLEAR_1111_FP32 = 0x06060606U,
RADV_DCC_GFX11_CLEAR_0001_UNORM = 0x08080808U,
RADV_DCC_GFX11_CLEAR_1110_UNORM = 0x0A0A0A0AU,
};
static uint32_t
radv_dcc_single_clear_value(const struct radv_device *device)
{
const struct radv_physical_device *pdev = radv_device_physical(device);
return pdev->info.gfx_level >= GFX11 ? RADV_DCC_GFX11_CLEAR_SINGLE : RADV_DCC_GFX9_CLEAR_SINGLE;
return pdev->info.gfx_level >= GFX11 ? GFX11_DCC_CLEAR_SINGLE : GFX9_DCC_CLEAR_SINGLE;
}
static void
@ -1247,10 +1231,10 @@ gfx8_get_fast_clear_parameters(struct radv_device *device, const struct radv_ima
/* comp-to-single allows to perform DCC fast clears without requiring a FCE. */
if (iview->image->support_comp_to_single) {
*reset_value = RADV_DCC_GFX9_CLEAR_SINGLE;
*reset_value = GFX9_DCC_CLEAR_SINGLE;
*can_avoid_fast_clear_elim = true;
} else {
*reset_value = RADV_DCC_GFX8_CLEAR_REG;
*reset_value = GFX8_DCC_CLEAR_REG;
*can_avoid_fast_clear_elim = false;
}
@ -1319,14 +1303,14 @@ gfx8_get_fast_clear_parameters(struct radv_device *device, const struct radv_ima
if (main_value) {
if (extra_value)
*reset_value = RADV_DCC_GFX8_CLEAR_1111;
*reset_value = GFX8_DCC_CLEAR_1111;
else
*reset_value = RADV_DCC_GFX8_CLEAR_1110;
*reset_value = GFX8_DCC_CLEAR_1110;
} else {
if (extra_value)
*reset_value = RADV_DCC_GFX8_CLEAR_0001;
*reset_value = GFX8_DCC_CLEAR_0001;
else
*reset_value = RADV_DCC_CLEAR_0000;
*reset_value = DCC_CLEAR_0000;
}
}
@ -1384,44 +1368,44 @@ gfx11_get_fast_clear_parameters(struct radv_device *device, const struct radv_im
if (all_bits_are_0 || all_bits_are_1 || all_words_are_fp16_1 || all_words_are_fp32_1) {
if (all_bits_are_0)
*reset_value = RADV_DCC_CLEAR_0000;
*reset_value = DCC_CLEAR_0000;
else if (all_bits_are_1)
*reset_value = RADV_DCC_GFX11_CLEAR_1111_UNORM;
*reset_value = GFX11_DCC_CLEAR_1111_UNORM;
else if (all_words_are_fp16_1)
*reset_value = RADV_DCC_GFX11_CLEAR_1111_FP16;
*reset_value = GFX11_DCC_CLEAR_1111_FP16;
else if (all_words_are_fp32_1)
*reset_value = RADV_DCC_GFX11_CLEAR_1111_FP32;
*reset_value = GFX11_DCC_CLEAR_1111_FP32;
return true;
}
if (desc->nr_channels == 2 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0xff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
*reset_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0x00) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
*reset_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 8) {
if (value.ub[0] == 0x00 && value.ub[1] == 0x00 && value.ub[2] == 0x00 && value.ub[3] == 0xff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
*reset_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.ub[0] == 0xff && value.ub[1] == 0xff && value.ub[2] == 0xff && value.ub[3] == 0x00) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
*reset_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
} else if (desc->nr_channels == 4 && desc->channel[0].size == 16) {
if (value.us[0] == 0x0000 && value.us[1] == 0x0000 && value.us[2] == 0x0000 && value.us[3] == 0xffff) {
*reset_value = RADV_DCC_GFX11_CLEAR_0001_UNORM;
*reset_value = GFX11_DCC_CLEAR_0001_UNORM;
return true;
} else if (value.us[0] == 0xffff && value.us[1] == 0xffff && value.us[2] == 0xffff && value.us[3] == 0x0000) {
*reset_value = RADV_DCC_GFX11_CLEAR_1110_UNORM;
*reset_value = GFX11_DCC_CLEAR_1110_UNORM;
return true;
}
}
if (iview->image->support_comp_to_single) {
*reset_value = RADV_DCC_GFX11_CLEAR_SINGLE;
*reset_value = GFX11_DCC_CLEAR_SINGLE;
return true;
}

26
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -133,32 +133,6 @@ enum si_has_ms {
MS_ON,
};
#define DCC_CODE(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x))
enum si_clear_code
{
/* Common clear codes. */
DCC_CLEAR_0000 = DCC_CODE(0x00), /* all bits are 0 */
DCC_UNCOMPRESSED = DCC_CODE(0xFF),
GFX8_DCC_CLEAR_0000 = DCC_CLEAR_0000,
GFX8_DCC_CLEAR_0001 = DCC_CODE(0x40),
GFX8_DCC_CLEAR_1110 = DCC_CODE(0x80),
GFX8_DCC_CLEAR_1111 = DCC_CODE(0xC0),
GFX8_DCC_CLEAR_REG = DCC_CODE(0x20),
GFX9_DCC_CLEAR_SINGLE = DCC_CODE(0x10),
GFX11_DCC_CLEAR_SINGLE = DCC_CODE(0x01),
GFX11_DCC_CLEAR_0000 = DCC_CLEAR_0000, /* all bits are 0 */
GFX11_DCC_CLEAR_1111_UNORM = DCC_CODE(0x02), /* all bits are 1 */
GFX11_DCC_CLEAR_1111_FP16 = DCC_CODE(0x04), /* all 16-bit words are 0x3c00, max 64bpp */
GFX11_DCC_CLEAR_1111_FP32 = DCC_CODE(0x06), /* all 32-bit words are 0x3f800000 */
/* Color bits are 0, alpha bits are 1; only 88, 8888, 16161616 */
GFX11_DCC_CLEAR_0001_UNORM = DCC_CODE(0x08),
/* Color bits are 1, alpha bits are 0, only 88, 8888, 16161616 */
GFX11_DCC_CLEAR_1110_UNORM = DCC_CODE(0x0A),
};
#define SI_IMAGE_ACCESS_DCC_OFF (1 << 8)
#define SI_IMAGE_ACCESS_ALLOW_DCC_STORE (1 << 9)
#define SI_IMAGE_ACCESS_BLOCK_FORMAT_AS_UINT (1 << 10) /* for compressed/subsampled images */