Commit graph

217399 commits

Author SHA1 Message Date
Olivia Lee
6eadcaa851 panvk: advertise VK_EXT_primitives_generated_query on v10+
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Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38547>
2026-01-21 09:03:34 +00:00
Olivia Lee
ab1a467331 panvk/csf: implement VK_EXT_primitives_generated_query primitive restart
The index buffer unrolling logic was based on asahi's implementation in
libagx/geometry.cl.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38547>
2026-01-21 09:03:34 +00:00
Faith Ekstrand
a0a232220f panvk: Map ro_sink_address_poly to an OOB address
Mali hardware handles a bunch of OOB conditions by using addresses with
the top bit set.  When the top bit is set, any load/store from a shader
will treat the address as OOB and read zero and discard writes.  We can
use this to implement ro_sink_address_poly.

Signed-off-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38547>
2026-01-21 09:03:34 +00:00
Olivia Lee
1ee08415cd panvk/csf: implement dynamic precomp dispatch size
To count primitives generated when primitive restart is enabled, we need
to dispatch a precomp shader with dimensions that depend on the indirect
draw count. For this, we need some kind of precomp dispatch mechanism
where the dimensions are determined at execution time. The standard
shape for this would be an "indirect precomp" dispatch which reads
dimensions from memory, but in this case that would be a little awkward
because the draw count is min(*draw_count_buffer, max_draw_count). So to
implement that with a typical indirect dispatch mechanism, we would need
to read the buffer, compare it with the max draw count, and then write
it back to scratch memory, just to read it again. To simplify this, I
went for a precomp dispatch mechanism where it just reading the
dimensions from the JOB_SIZE registers set by the caller, which can use
whatever CS code it wants to calculate them.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38547>
2026-01-21 09:03:34 +00:00
Olivia Lee
1bdd640d83 panvk/csf: implement VK_EXT_primitives_generated_query except primitive restart
Primitive restart requires scanning the index buffer to determine how
many primitives are present, and will be handled in a later commit.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Christoph Pillmayer <christoph.pillmayer@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38547>
2026-01-21 09:03:33 +00:00
Olivia Lee
8f5d9f6fd7 poly: add messages to static_assert calls
static_assert required a message argument until C23. Adding it fixes
the debian-clang CI jobs.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38547>
2026-01-21 09:03:33 +00:00
Erico Nunes
ca1d59d813 ci: lima farm maintenance
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39388>
2026-01-21 08:27:01 +00:00
Daivik Bhatia
92fc9719bb v3dv: improve barrier handling for secondary command buffers
Use v3dv_job_apply_barrier_state to consume pending barriers when
executing secondary command buffers. This ensures we only serialize
against relevant stages, addressing FIXME.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39278>
2026-01-21 07:37:49 +00:00
Samuel Pitoiset
de64c7238a ac/nir: fix computing cube derivatives when the major axis is negative
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This corresponds to the face 1.0, 3.0 or 5.0.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39303>
2026-01-21 07:12:34 +00:00
Qiang Yu
4708eb85d7 radv: fix primitive restart gpu hang for pre gfx10
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PAL always set WD_SWITCH_ON_EOP for pre gfx10 when primitive
restart is enabled to prevent gpu hang.

It only happens when specific index stream with primitive
restart. Since we don't know what's the exact problem,
just follow PAL to disable 4x primitive rate when primitive
restart is enabled.

GFX10+ does not use this function.

Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39292>
2026-01-21 02:38:26 +00:00
Qiang Yu
7d73ea20ec radeonsi: fix primitive restart gpu hang for pre gfx10
PAL always set WD_SWITCH_ON_EOP for pre gfx10 when primitve
restart is enabled to prevent gpu hang.

It only happens when specific index stream with primitive
restart. Since we don't know what's the exact problem,
just follow PAL to disable 4x primitive rate when primitive
restart is enabled.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14629
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39292>
2026-01-21 02:38:25 +00:00
Arzaq Naufail Khan
dc702671d9 anv: eliminate dead code
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39400>
2026-01-21 01:21:55 +00:00
Thong Thai
c4f05bdf60 frontends/va: include picture_*.c based on selected codec
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Only add the appropriate picture_{h264,h264_enc,vc1,...}.c file when the
corresponding codec is enabled via the -Dvideo-codecs flag.

Add stub functions to va_private.h, so that the code in decode.c and
encode.c remains untouched.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39354>
2026-01-20 22:42:08 +00:00
Thong Thai
f4959c16c8 meson: add mpeg12dec as a video-codec
Add mpeg12dec as a selectable video-codec and add a corresponding check
to vl_codec_supported.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39354>
2026-01-20 22:42:08 +00:00
Thong Thai
f9c1ba8c17 meson: add jpeg as a video-codec
Add jpeg as a selectable video-codec and add a corresponding check to
vl_codec_supported.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39354>
2026-01-20 22:42:08 +00:00
Sagar Ghuge
8e85607130 anv/rt: Drop atomic operations on opacity flags
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Each node has their own opacity bits, so we don't need to track these
opacity flags at header level.

This commit also fixes the instance flag. Instance flag is 8bit wide,
but we were always using 4 lower bits.

Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39053>
2026-01-20 22:20:28 +00:00
Sagar Ghuge
61691034ac anv/rt: Don't always set disableOpacityCull bit
Setting this bit always might hurt performance. It might forces
traversal to treat all leafs always valid.

Cc: mesa-stable
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39053>
2026-01-20 22:20:28 +00:00
Natalie Vock
e8f1dc687c aco: Use parameter assignment hints for any-hit shaders
Query the signature of the traversal function stored in the any-hit
shader and make the parameter locations between the two match up, to
remove unnecessary movs inside the traversal loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
a32709674a aco: Add parameter assignment hints
Parameter assignment hints allow to influence parameter register
assignment logic with user-specified affinities. If there is an affinity
declared for a parameter, the assignment logic will try to match the
registers a parameter and its affinity are assigned.

It also allows to hint that certain registers are not suitable for
assigning parameters to and should be avoided.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
2d6ecf303a aco: Add and use nir_abi_to_aco helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
30f6eacfad radv/rt: Call ahit/isec shaders
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
a03e9287c3 radv/rt: Compile ahit/isec shaders to asm
We can express any-hit/intersection shaders as functions, too.
Any-hit/Intersection shaders need the usual parameters like launch
IDs/descriptor data/ray properties, origin, direction/etc., but also
some special parameters related to traversal state. Any-hit/intersection
shaders need to return whether the hit was accepted and/or traversal
should be terminated, as well as the intersection T value (for
intersection shaders). Both any-hit and intersection shaders also need
to be passed hit attributes via parameters. Closest-Hit shaders need
those too, but we pass them out-of-band via LDS. LDS is used for the
traversal stack when any-hit/intersection shaders, so we need to pass
them via parameters.

Hit attributes are similar to ray payloads in the sense that they're
dynamically sized depending on how much space the application uses.
However, unlike ray payloads, hit attribute sizes have a strict upper
bound of 8 dwords. To make managing parameters easier, we put all hit
attributes in a single vector parameter with 0-8 components. This
prevents having a function with two sets of arbitrary numbers of
parameters.

This commit sets up ahit/isec function signatures and implements
lowering for ahit/isec-specific intrinsics in the context of these
functions. Subsequent commits will merely have to call into these
functions to execute a separate-compiled any-hit/intersection shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:55 +00:00
Natalie Vock
e74e0983a7 radv/rt: Fix terminate_ray handling for intersection shaders
terminate_ray should only return from any-hit shaders, it should not
skip the intersection shader. If we insert a nir_jump_return when
processing the already-inlined any-hit shader, the intersection shader
will be skipped.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
646d3b9645 radv/nir: Make nir_lower_intersection_shader public
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
1fb005b487 radv/nir: Add and use radv_nir_return_param_from_type helper
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
bde7bebc01 radv/rt: Don't consider non-internal INTERSECTION shaders as the traversal shader
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
b52adac42c aco: Tweak ABI register param limits
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Natalie Vock
7a2f050daa aco: Put boolean parameters inside SGPRs
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39314>
2026-01-20 21:49:54 +00:00
Lionel Landwerlin
3d2a696763 brw: treat inline parameters like UNIFORM
Makes a bunch of copy propagation and other passes work much better.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39382>
2026-01-20 21:25:53 +00:00
Lionel Landwerlin
1d1866a84b brw: apply same workaround to spawn than trace opcode
Working around BRW's limitations

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39382>
2026-01-20 21:25:52 +00:00
Lionel Landwerlin
0e9453291c brw: improve push constant loading using base offsets
Xe2+ only

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39382>
2026-01-20 21:25:52 +00:00
Lionel Landwerlin
c1ef494b08 brw: add missing base offset decoding
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39382>
2026-01-20 21:25:52 +00:00
Faith Ekstrand
b332b5cc46 panfrost: Add a few missing license blocks
These are based on digging through the git history on each file.

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39397>
2026-01-20 20:49:33 +00:00
Faith Ekstrand
08d7d9cfa4 pan/genxml: Add lisence blocks to the XML files
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39397>
2026-01-20 20:49:33 +00:00
Faith Ekstrand
934cfc0223 panfrost: SPDX everything
This replaces all full lisence headers with SPDX identifiers and
generally makes things more consistent.  I've also dropped the few
remaining author tags.  If someone wants to know who wrote a bit of
code, `git blame` is going to be way more accurate than author tags
anyway.

Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39397>
2026-01-20 20:49:33 +00:00
Faith Ekstrand
533b8170b3 ci: Mark fbo-blending-format-quirks as a fail on G52
This reverts a single hung from 669ddc5241 ("pan/blend: Use the blend
builder helpers instead of nir_lower_blend()").  That commit did fix the
test on a bunch of platforms, just not G52.

Fixes: 669ddc5241 ("pan/blend: Use the blend builder helpers instead of nir_lower_blend()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39397>
2026-01-20 20:49:33 +00:00
Serdar Kocdemir
9ef6ed5531 gfxstream: Add VK_EXT_frame_boundary support
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Also add codegen for VK_EXT_blend_operation_advanced

Test: dEQP-VK.api.frame_boundary.*

Reviewed-by: Aaron Ruby <aruby@qnx.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39360>
2026-01-20 20:27:10 +00:00
Jason Macnak
7dfb009601 gfxstream: Reland "Remove unnecessary tag to simplify perfetto trac..."
Reason for reland: relanding with fix

Reviewed-by: Aaron Ruby <aruby@qnx.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39360>
2026-01-20 20:27:10 +00:00
Jason Macnak
bf55e43f30 gfxstream: Reland "Add Vulkan func/structs for passing debugging da..."
Reason for reland: relanding with host side fix

Reviewed-by: Aaron Ruby <aruby@qnx.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39360>
2026-01-20 20:27:10 +00:00
Sharjeel Khan
01bd71788d gfxstream: [C++23] Fixes for C++23 issues
C++23 removed certain transitive includes so you need to add C++ headers
directly to utilize their functions and classes. We add cstdlib header
for abort.

Errors:
external/mesa3d/src/gfxstream/guest/vulkan_enc/goldfish_vk_counting_guest.cpp:9505:13:
error: use of undeclared identifier 'abort'
 9505 |             abort();

Test: m vulkan.ranchu

Reviewed-by: Aaron Ruby <aruby@qnx.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39360>
2026-01-20 20:27:10 +00:00
anonymix007
7300aa34a0 tgsi/nir: Store output variables before each TGSI_OPCODE_RET
Fixes: 885323ea3a
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39379>
2026-01-20 19:54:23 +00:00
Yiwei Zhang
c031bbd4b6 vulkan/wsi: improve present wait enablement tracking
Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39322>
2026-01-20 19:13:33 +00:00
Yiwei Zhang
669503e404 vulkan/wsi: rename khr_present_wait to has_present_wait
Trivial refactor to aligns with surrounding codes and avoid confusions.

Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39322>
2026-01-20 19:13:33 +00:00
Yiwei Zhang
b986250b69 vulkan/wsi: fix present wait support and present id creation condition
Common wsi should only create that semaphore if present wait is enabled.
Drivers may only advertise KHR_present_wait2 w/o KHR_present_wait. So
the common wsi core has to check for both.

Fixes: bf285c3be9 ("vulkan/wsi: Add basic support for PresentWait2")
Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39322>
2026-01-20 19:13:33 +00:00
Yiwei Zhang
be9caf8ed6 vulkan/wsi: avoid host stage when blit to foreign queue
For mitigating the below VVL violation:

> VUID-vkCmdPipelineBarrier-srcStageMask-09634
>
> vkCmdPipelineBarrier(): dstStageMask is VK_PIPELINE_STAGE_HOST_BIT
> but srcQueueFamilyIndex (0) != dstQueueFamilyIndex (4294967293).
>
> The Vulkan spec states: If either srcStageMask or dstStageMask
> includes VK_PIPELINE_STAGE_HOST_BIT, for any element of
> pBufferMemoryBarriers, srcQueueFamilyIndex and dstQueueFamilyIndex
> must be equal

Fixes: 153857fb64 ("vulkan/wsi: amend barriers for blit dst buffer going to foreign queue")
Reviewed-by: Hans-Kristian Arntzen <post@arntzen-software.no>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39322>
2026-01-20 19:13:32 +00:00
Utku Iseri
5a5a87ecdb zink: use gfx_pipeline_state.dirty as a pipeline update condition
Without this, non-dynamically-supported state changes that require a pipeline
change (like blend states without full_ds3) that happen in between drawcalls
get ignored unless another one of the conditions also happened to be true.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39381>
2026-01-20 18:48:27 +00:00
Utku Iseri
d27dd392b8 zink: don't set pipeline_state.dirty for halfz with full_ds3
This helps reduce the upcoming pipeline check conditions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39381>
2026-01-20 18:48:27 +00:00
Utku Iseri
7103457acb zink: don't set gfx_pipeline_state.dirty if min_samples didn't change
This helps reduce the upcoming pipeline check conditions.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39381>
2026-01-20 18:48:27 +00:00
Utku Iseri
f2273866b1 zink: set gfx_pipeline_state.dirty for blit rp changes
This was being hidden by set_min_samples always setting
the dirty flag during blit state save/restore.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39381>
2026-01-20 18:48:27 +00:00
Samuel Pitoiset
71f5434142 radv: optimize layered fast clear colors when comp-to-single is supported
comp-to-single is supported since GFX10, it's a new type of DCC fast
clear which doesn't require FCE and doesn't require to set fast clear
registers (ie. comp-to-reg). This means that it's possible to fast clear
even if not all slices are bound, because the clear code is stored in
the main image.

This improves performance in Dirt Rally 2.0 by +2-5%. Other games that
have layered clears would also benefit on GFX10+.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39394>
2026-01-20 18:28:59 +00:00