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brw: treat inline parameters like UNIFORM

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Makes a bunch of copy propagation and other passes work much better.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39382>
This commit is contained in:
Lionel Landwerlin 2026-01-19 10:49:40 +02:00 • committed by Marge Bot
parent 1d1866a84b
commit 3d2a696763
3 changed files with 26 additions and 20 deletions
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9
src/intel/compiler/brw/brw_from_nir.cpp
View file

@ -4313,15 +4313,12 @@ brw_from_nir_emit_cs_intrinsic(nir_to_brw_state &ntb,
break;
case nir_intrinsic_load_inline_data_intel: {
const brw_cs_thread_payload &payload = s.cs_payload();
unsigned inline_stride = brw_type_size_bytes(dest.type);
for (unsigned c = 0; c < instr->def.num_components; c++) {
xbld.MOV(offset(dest, xbld, c),
retype(
byte_offset(payload.inline_parameter,
nir_intrinsic_base(instr) +
c * inline_stride),
dest.type));
byte_offset(brw_uniform_reg(BRW_INLINE_PARAM_REG, dest.type),
nir_intrinsic_base(instr) +
c * inline_stride));
}
break;
}

3
src/intel/compiler/brw/brw_reg.h
View file

@ -70,6 +70,9 @@ struct intel_device_info;
#define BRW_SWIZZLE_Z 2
#define BRW_SWIZZLE_W 3
/** Special value to treat inline parameter values like UNIFORM */
#define BRW_INLINE_PARAM_REG (65535)
#define BRW_SWIZZLE4(a,b,c,d) (((a)<<0) | ((b)<<2) | ((c)<<4) | ((d)<<6))
#define BRW_GET_SWZ(swz, idx) (((swz) >> ((idx)*2)) & 0x3)

34
src/intel/compiler/brw/brw_shader.cpp
View file

@ -750,26 +750,32 @@ brw_shader::assign_curb_setup()
/* Map the offsets in the UNIFORM file to fixed HW regs. */
foreach_block_and_inst(block, brw_inst, inst, cfg) {
for (unsigned int i = 0; i < inst->sources; i++) {
if (inst->src[i].file == UNIFORM) {
if (inst->src[i].file != UNIFORM)
continue;
struct brw_reg brw_reg;
if (inst->src[i].nr == BRW_INLINE_PARAM_REG) {
brw_reg = cs_payload().inline_parameter;
} else {
assert(inst->src[i].nr < 64);
used |= BITFIELD64_BIT(inst->src[i].nr);
assert(inst->src[i].nr < this->push_data_size);
struct brw_reg brw_reg = brw_vec1_grf(payload().num_regs +
inst->src[i].nr, 0);
brw_reg.abs = inst->src[i].abs;
brw_reg.negate = inst->src[i].negate;
brw_reg = brw_vec1_grf(payload().num_regs + inst->src[i].nr, 0);
}
/* The combination of is_scalar for load_uniform, copy prop, and
* lower_btd_logical_send can generate a MOV from a UNIFORM with
* exec size 2 and stride of 1.
*/
assert(inst->src[i].stride == 0 || inst->exec_size == 2);
inst->src[i] = byte_offset(
retype(brw_reg, inst->src[i].type),
inst->src[i].offset);
}
brw_reg.abs = inst->src[i].abs;
brw_reg.negate = inst->src[i].negate;
/* The combination of is_scalar for load_uniform, copy prop, and
* lower_btd_logical_send can generate a MOV from a UNIFORM with exec
* size 2 and stride of 1.
*/
assert(inst->src[i].stride == 0 || inst->exec_size == 2);
inst->src[i] = byte_offset(
retype(brw_reg, inst->src[i].type),
inst->src[i].offset);
}
}