Commit graph

695 commits

Author SHA1 Message Date
Marek Olšák
6d1ab77a8f radeonsi: rewrite inlinable uniform states for shader keys in si_context
directly update the shader keys in si_context

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
aed93eb991 radeonsi: update the VS shader key in set & bind functions and remove memsets
This decreases overhead of si_update_shaders and overall driver overhead.

The VS shader key portion related to VS inputs is updated in set & bind
functions. Other fields related to outputs are still updated
in si_shader_selector_key.

Now that all modified fields are set to 0 when not needed, and remove
the memsets.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
74a0c9bd51 radeonsi: clean up and clear VS shader key fields related to outputs
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
dbdde903bb radeonsi: update most of the PS shader key in set & bind functions
This decreases overhead of si_update_shaders and overall driver overhead.

There is only one function that depends on the rasterized primitive type,
and thus it can't be moved to set & bind functions.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
7e3c03bc6a radeonsi: ignore blitter when computing the PS shader key
it doesn't have any effect

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
00d1d947ea radeonsi: divide si_update_ps_shader_key into many separate functions
they will be used in bind functions etc.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
59072ee484 radeonsi: don't memset part in si_update_ps_shader_key
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
60580c04c0 radeonsi: don't memset mono and opt in si_update_ps_shader_key
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
46bda71a54 radeonsi: move PS shader key code into a separate function
There is reordering and new comments.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
a912c80439 radeonsi: sink memsets and disable uniform inlining in si_shader_selector_key
to facilitate refactoring. Uniform inlining will be re-enabled later.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
0b1fd84950 radeonsi: handle NO_OPT_VARIANT in si_shader_select_with_key
so as not to change the keys in si_context

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
03b5a94258 radeonsi: add const to the key parameter in si_shader_select_with_key
The keys will match the current state, so we shouldn't change them.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12343>
2021-09-14 15:24:11 +00:00
Marek Olšák
eddb65ffb0 radeonsi: don't use NGG passthrough if culling is possible for better perf
Switching NGG passthrough on/off decreases performance because it causes
context rolls.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
2021-09-10 23:32:03 +00:00
Marek Olšák
64a06f8167 radeonsi: skip setting some PGM_HI registers by switching to 32-bit addresses
Other registers benefit from consecutive register offsets for the smallest
command buffer size.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
2021-09-10 23:32:03 +00:00
Marek Olšák
576f8394db radeonsi: remove the primitive discard compute shader
It doesn't always work, it's only useful on gfx9 and older, and it's too
complicated.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4011

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
2021-09-10 23:32:03 +00:00
Marek Olšák
ece92ecc35 radeonsi: ignore the vertex element count in si_shader_selector_key_vs
It's always at least num_inputs, so just use num_inputs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
2021-09-10 23:32:02 +00:00
Marek Olšák
0186c788b6 radeonsi: don't set prefer_mono for fetched instance divisors
It's not necessary because the overhead is very low and the comment isn't
true anymore. (the divisions are fast now)

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12812>
2021-09-10 23:32:02 +00:00
Marek Olšák
f28552b804 radeonsi: don't use SQ_NON_EVENT before GE_PC_ALLOC for better perf on Navi1x
SQ_NON_EVENT was originally meant to fix a perf issue on Navi1x, but using
the event actually makes the perf worse.

This improves perf for viewperf/snx.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:58 +00:00
Marek Olšák
0aed2d0cd3 radeonsi: stop using AC_EXP_PARAM_UNDEFINED because it's not useful
Just use AC_EXP_PARAM_DEFAULT_VAL_0000 to keep things simple.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:57 +00:00
Marek Olšák
2027831aaa radeonsi: inline si_get_alpha_test_func
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:57 +00:00
Marek Olšák
c005b2cd4b radeonsi: move as_ls/es/ngg setting out of si_shader_selector_key
Do it when we bind shaders.

The advantages are:
- no need to memset the fields when any shader variant state is changed
  (e.g. culling on/off)
- no need to recompute the fields every time that happens

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:57 +00:00
Marek Olšák
5a8a716168 radeonsi: move si_vgt_stages_key determination into si_update_vgt_shader_config
This simplifies si_update_shaders. It also makes it more obvious that
si_update_shaders could become a C++ template one day.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:57 +00:00
Marek Olšák
ec37db756e radeonsi: remove stages_key parameter from si_shader_selector_key
no change in behavior

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:57 +00:00
Marek Olšák
08310f85ae radeonsi: remove instancing support from the prim discard compute shader
It's not important for workstation apps on Vega.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
2021-09-01 00:42:57 +00:00
Pierre-Eric Pelloux-Prayer
9fe8ae3fcd radeonsi: don't create an infinite number of variants
If a shader has code like this:

   uniform float timestamp;
   ...
   if (timestamp > 0.0)
      do_something()

And timestamp is modified each frame, we'll end up generating a new
variant per frame.

This commit introduces a hard limit on the number of variants we generate
for a single shader.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5121
Fixes: b7501184b9 ("radeonsi: implement inlinable uniforms")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12138>
2021-08-09 10:26:54 +00:00
Yogesh mohan marimuthu
be9ca62247 radeonsi: remove redundant setting scratch_state atom dirty
Whenever scratch buffer is allocated, current spi_tmpring_size and
previous spi_tmpring_size cannot be same and hence scratch_state will be
set dirty as part of "if (spi_tmpring_size != sctx->spi_tmpring_size)".
Removing redundant dirty bit sat while allocating scratch buffer.

Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11900>
2021-07-16 23:08:00 +00:00
Marek Olšák
b2397c394d ac,radeonsi: move late alloc computation into common code and shader states
This also fixes a rare deadlock when a scratch buffer is used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>
2021-07-08 18:37:41 +00:00
Marek Olšák
66f254b4e6 radeonsi,radv: fix a late alloc deadlock with <= 6 CUs per SA
We should always prevent 1 CU from executing VS and GS waves
to prevent a deadlock.

Fixes: c377f45c18 "radeonsi/gfx10: rewrite late alloc computation"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>
2021-07-08 18:37:41 +00:00
Marek Olšák
786678a017 radeonsi: restructure si_get_vs_vgpr_comp_cnt for readability
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11102>
2021-06-21 19:03:29 +00:00
Mike Blumenkrantz
a3a6611e96 util/queue: add a global data pointer for the queue object
this better enables object-specific (e.g., context) queues where the owner
of the queue will always be needed and various pointers will be passed in
for tasks

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11312>
2021-06-16 15:10:09 -04:00
Marek Olšák
a0fcd37731 radeonsi: remove a twice duplicated workaround for VERT_GRP_SIZE
This enables better lane occupancy.

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
2021-05-25 16:15:44 +00:00
Marek Olšák
c8e8979d6b radeonsi: fix the fast launch vert/prim thread counts if they are trimmed
This fixes the case when the counts were out of sync because one of them
was decreased.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10813>
2021-05-25 16:15:44 +00:00
Marek Olšák
0e8100bf58 radeonsi: simplify the NGG culling vertex count heuristic
This removes another chip-specific switch.
It enables a lower threshold on Navi1x, which should be fine.

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
2021-05-24 17:41:34 +00:00
Samuel Pitoiset
726cb2d6f6 ac: ac_gpu_info::has_vgt_flush_ngg_legacy_bug
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10911>
2021-05-21 19:46:56 +00:00
Marek Olšák
c53f25b668 radeonsi: kill 16-bit VS outputs if PS doesn't use them or doing Z-only draw
The kill_outputs logic uses our internal IO indices. Just add indices for
16-bit varyings. We don't have enough free indices to use, but we can reuse
the indices that GLES doesn't have. Those are all the legacy desktop GL
varyings.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
2021-04-13 21:10:43 -04:00
Marek Olšák
7db43960f6 radeonsi: implement 16-bit VS->PS varyings
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9051>
2021-04-13 21:10:43 -04:00
Pierre-Eric Pelloux-Prayer
8c6a64c9b0 radeonsi/rgp: export compute shader programs
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10105>
2021-04-12 14:27:29 +02:00
Axel Davy
ff6f11acdc radeonsi: fix leak when the in-memory cache is full
When the hw_binary is not put in the in-memory
cache it must be freed.

Fixes: 8283ed65cf ("radeonsi: Limit the size of the in-memory shader cache")

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9587>
2021-03-17 21:05:06 +00:00
Axel Davy
8283ed65cf radeonsi: Limit the size of the in-memory shader cache
The in-memory shader cache can get significantly
huge in some rare cases.
Limit its size to 64MB on 32 bits, and 1GB else.

Signed-off-by: Axel Davy <davyaxel0@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9578>
2021-03-13 21:51:38 +00:00
Dave Airlie
8027a7ba8a shader_info: convert textures_used to a bitset.
For now keep it a bitset of 1 32-bit dword.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9456>
2021-03-10 06:16:09 +10:00
Pierre-Eric Pelloux-Prayer
c276bde34a radeonsi/sqtt: export shader code to RGP
With these changes the shader code is visible in RGP.

Vk pipeline feature is emulated using si_update_shaders: when shaders are
updated we compute a sha1 of their code and use it as a pipeline hash.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9277>
2021-03-05 13:10:11 +00:00
Pierre-Eric Pelloux-Prayer
0e97d817f5 radeonsi: properly set SPI_SHADER_PGM_HI_ES
When not using S_00B324_MEM_BASE the value isn't properly truncated.

Cc: mesa-stable
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9277>
2021-03-05 13:10:11 +00:00
Marek Olšák
c97ebe1461 radeonsi: don't index si_context::shaders with enum gl_shader_stage
Fixes: a8373b3d38 "radeonsi: store si_context::xxx_shader members in union"

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9313>
2021-03-02 01:14:44 +00:00
Marek Olšák
8288882965 radeonsi: set MEM_ORDERED optimally
It must be 1 only if both sampler and non-sampler VMEM instructions
that return something are used. BVH counts as a sampler instruction.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9028>
2021-02-17 04:49:24 -05:00
Pierre-Eric Pelloux-Prayer
a8373b3d38 radeonsi: store si_context::xxx_shader members in union
This allows to access them individually (sctx->shader.ps) or
using array indexing (sctx->shaders[PIPE_SHADER_FRAGMENT]).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8869>
2021-02-17 09:11:46 +00:00
Marek Olšák
61fd8fc10b radeonsi: skip s_sendmsg(gs_alloc_req) for NGG passthrough on new chips
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8892>
2021-02-13 04:56:05 +00:00
Marek Olšák
34114e1dcb radeonsi: tune NGG shader culling vertex threshold for each chip
These are based on my testing and estimation.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Marek Olšák
ffbf3a5f8b radeonsi: simplify the NGG culling condition in si_draw_vbo
Changes:

- disallow NGG culling for GS, fast launch for tess using template args
  (GS can't do NGG culling, tess can't do fast launch)

- skip checking current_rast_prim with tessellation
  (bake the condition into ngg_cull_vert_threshold)

- use only 1 vertex count threshold for enabling NGG shader culling
  to simplify it. I think it doesn't have a big impact. The threshold
  computation depends on more parameters than just fast launch.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Marek Olšák
7581743510 radeonsi: set current_rast_prim at bind time for tess and GS
It doesn't have to be done in draw_vbo.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8434>
2021-02-02 05:42:32 +00:00
Marek Olšák
11293d71f2 radeonsi: delete si_pm4_delete_state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8794>
2021-01-30 15:41:23 -05:00