radeonsi: don't use SQ_NON_EVENT before GE_PC_ALLOC for better perf on Navi1x

SQ_NON_EVENT was originally meant to fix a perf issue on Navi1x, but using
the event actually makes the perf worse.

This improves perf for viewperf/snx.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12656>
This commit is contained in:
Marek Olšák 2021-08-18 15:21:28 -04:00 committed by Marge Bot
parent 9fb77745f5
commit f28552b804
2 changed files with 0 additions and 13 deletions

View file

@ -70,12 +70,6 @@ si_create_shadowing_ib_preamble(struct si_context *sctx)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (sctx->chip_class == GFX10) {
/* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0));
si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
}
if (sctx->screen->dpbb_allowed) {
si_pm4_cmd_add(pm4, PKT3(PKT3_EVENT_WRITE, 0, 0));
si_pm4_cmd_add(pm4, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));

View file

@ -983,13 +983,6 @@ static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
radeon_begin(cs);
if (sctx->chip_class == GFX10) {
/* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
}
radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
radeon_end();