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radeonsi: simplify the NGG culling vertex count heuristic

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This removes another chip-specific switch.
It enables a lower threshold on Navi1x, which should be fine.

Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10878>
This commit is contained in:
Marek Olšák 2021-05-06 20:43:34 -04:00 • committed by Marge Bot
parent a76ec17f12
commit 0e8100bf58
1 changed files with 1 additions and 16 deletions
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17
src/gallium/drivers/radeonsi/si_state_shaders.c
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@ -2849,22 +2849,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
sscreen->info.chip_class == GFX10_3 ||
(sscreen->info.chip_class == GFX10 &&
sscreen->info.is_pro_graphics)) {
/* Rough estimates. */
switch (sctx->family) {
case CHIP_NAVI10:
case CHIP_NAVI12:
case CHIP_SIENNA_CICHLID:
sel->ngg_cull_vert_threshold = 511;
break;
case CHIP_NAVI14:
case CHIP_NAVY_FLOUNDER:
case CHIP_DIMGREY_CAVEFISH:
case CHIP_VANGOGH:
sel->ngg_cull_vert_threshold = 255;
break;
default:
assert(!sscreen->use_ngg_culling);
}
sel->ngg_cull_vert_threshold = sscreen->info.num_se >= 3 ? 511 : 255;
}
} else if (sel->info.stage == MESA_SHADER_TESS_EVAL) {
if (sel->rast_prim == PIPE_PRIM_TRIANGLES &&