If this gets run right after something which uses
VK_VERTEX_INPUT_RATE_INSTANCE on its first vertex binding, we could end
up in serious trouble.
Fixes: 3d9747780b "anv: Add a helper for doing buffer copies with..."
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5090>
We create a stub never-signaled seqno to force the iris_fence to use the
fence fd, but we need to fully initialise the iris_seqno struct so that
the unset pointers are NULL and we do not try to destroy them later.
==38644== Conditional jump or move depends on uninitialised value(s)
==38644== at 0xF7FBFAA: pipe_resource_reference (u_inlines.h:142)
==38644== by 0xF7FC22F: iris_seqno_destroy (iris_seqno.c:38)
==38644== by 0xF7E8930: iris_seqno_reference (iris_seqno.h:89)
==38644== by 0xF7E8BC3: iris_fence_destroy (iris_fence.c:131)
==38644== by 0xF7E8C41: iris_fence_reference (iris_fence.c:143)
==38644== by 0xEF24525: dri2_destroy_fence (dri_helpers.c:176)
==38644== by 0x4865DC2: dri2_egl_unref_sync (egl_dri2.c:3302)
==38644== by 0x48661E8: dri2_destroy_sync (egl_dri2.c:3433)
==38644== by 0x4855BA4: _eglDestroySync (eglapi.c:1952)
==38644== by 0x4855CF5: eglDestroySyncKHR (eglapi.c:1972)
==38644== by 0x402628: test_cleanup (egl_khr_fence_sync.c:232)
==38644== by 0x40421E: test_eglCreateSyncKHR_native_from_fd (egl_khr_fence_sync.c:1521)
Closes: #2909
Fixes: fd1907efb3 ("iris: Convert fences to using lightweight seqno")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5004>
Older kernels did not support `MSM_INFO_GET_IOVA`. But this is only
required for (a) clover (ie. `fd_set_global_binding()`) and drm paths
that are limited to newer kernels. So move the location of the assert
to fix new userspace on old kernels.
Fixes: c9e8df61dc ("freedreno: Initialize the bo's iova at creation time.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5081>
"softpin" mode was introduced in the same kernel as the 'DUMP' flag. So
if we are using the legacy non-softpin path, clear the dump flag. OTOH
the 'DUMP' flag isn't quite so needed on older kernels, since we would
get all cmdstream, even SDS stateobjs, dumped regardless, as they would
have cmd table entries.
Fixes: b2c23b1e48 ("freedreno: Mark all ringbuffer BOs as to be dumped on crash.")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5081>
We don't support any timer queries, so stop lying about our
ability to do so.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5086>
A3xx apparently has higher alignment requirements than later gens for
indirect const uploads. It also has fewer of them. Add compiler
parameters for both settings, and set accordingly for a3xx and a4xx+.
This fixes all the ubo test failures caused by this optimization.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
Caused assertions to trip even though everything was fine. The number of
constants can be equal to length, so we need less-than-or-equal.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
In commit 5d8f40a53a, the change was done incorrectly, switching from
max_const to constlen + 1. Instead it should have been constlen - 1,
which is the analog to the former max_const.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5077>
This causes failures on a3xx resulting in the non-sensical dEQP failures
on packUnorm2x16. The same test uses ldlv on a4xx+, so just disallow
(sat) on bary.f on all generations.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5074>
Rendering doesn't work, but having the format in place avoids an assert
when selecting the texture format in st_format. I believe it's required
for GLES3, so more tracing is required to determine what bit we're
missing to make rendering work.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5073>
This fixes a number of dEQP tests:
dEQP-GLES3.functional.fbo.blit.conversion.r8*
dEQP-GLES3.texture.specification.basic_teximage2d.r8*
and others. The reason why this enum showed up in traces for R8 is that
it was an "upgraded" texture to R8G8.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5073>
Since commit 8b8af6d398 there is a
performance regression in dirt 4 on picasso APUs.
The game ends up feeding a large value into this which overflows on the
conversion to 16bit float. With the old implementation (which now lives
in util_float_to_half_rtz) it would be clamped to inf-1, while the new
one returns inf. This causes a performance hit somehow at some point
down the line.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 8b8af6d398 "gallium/util: Switch util_float_to_half to _mesa_float_to_half()'s impl."
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5062>
Move steps from lowering to emit, since they can be done earlier in a
single place, rather than in two-steps.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
ppir doesn't register successors in other blocks, and causes
ppir_node_has_single_succ to be unreliable as it might return true for
nodes with successors in other blocks.
This is bad for optimization passes that try to pipeline registers or
avoid insertion of movs, as that can generally only be done for nodes
with a single user.
As of now, ppir can't just start adding successors in other blocks as
that breaks the scheduling code.
So this patch is a little hacky but enables pipelining optimizations
during lowering. It can hopefully be removed during future scheduler
rework.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
In some paths where ppir_emit_cf_list is called, compilation errors such
as in unsupported features were not being handled, allowing compilation
to continue and fail at some random point later.
Handle them properly so compilation aborts in the expected way rather
than what may look like a compiler crash/bug.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4975>
Any system that provides `/dev/urandom` should be allowed to try to use it.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2316>
When the caller asked for a randomised_seed, we should fall back to the
time-based seed instead of the fixed seed.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2316>
Add new IRIS_DIRTY_STENCIL_REF dirty flag which would help us to trigger
separate 3DSTATE_WM_DEPTH_STENCIL packet using modify disable fields.
Instead of merging two packets into one in order to build
3DSTATE_WM_DEPTH_STENCIL state, set_stencil_ref can use
IRIS_DIRTY_STENCIL_REF bit and bind_zsa_state can use
IRIS_DIRTY_WN_DEPTH_STENCIL, both could cause packet to happen with
available information using modify disable bits which allow us to
construct packet by ignoring set of fields.
v2: (Kenneth Graunke)
- Fix condition ordering.
- Club GEN cases.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3688>
