Commit graph

104587 commits

Author SHA1 Message Date
Rob Clark
6b4397feab freedreno/a6xx: fix debug build crash
Porting 0c8d9e923a to a6xx.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-09-05 13:38:43 -04:00
Dylan Baker
d25a27ec56 meson: Print a message about why a libdrm version was selected
We require a single version of libdrm for all of our libdrm
dependencies (core and driver), but the way this is structured can make
the error message less than helpful, as one driver might be the one
setting the libdrm requirement, while another might be the one that
generates the version failure.

This adds a simple message to the output announcing which libdrm module
set the version, which might be more helpful.

v2: - Use message suggested by Eric Engstrom

Fixes: c445b1d56f
       ("meson: Use the same version for all libdrm checks")
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-09-05 10:32:51 -07:00
Charmaine Lee
af104ad799 svga: rename face to layer_face
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-05 11:22:42 -06:00
Brian Paul
e334e104d0 svga: encode sample count in resource declarations
No regressions before the corresponding host-side change.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
2018-09-05 11:22:42 -06:00
Charmaine Lee
49678e9e49 svga: sync with upstream changes to surface flags
SVGA device now supports 64 bits surface flags. This patch
updates the winsys interface to allow 64 bits surface flags.
The linux winsys layer will for now only honor the lower 32 bits of
the surface flags.

Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-05 11:22:42 -06:00
Neha Bhende
4310649ccb svga: avoid try_blit() for some depth formats on non vgpu10.
On non vgpu10, driver doesn't support util_blitter_blit for SVGA3D_Z_D16,
SVGA3D_Z_D24x8, SVGA3D_Z_D24S8. Patch fixes following piglit tests regression on hwv8 caused
by commit 27bf35caea5e:
spec@arb_depth_texture@fbo-depth-gl-depth-component16-blit
spec@arb_depth_texture@fbo-depth-gl-depth-component24-blit
spec@arb_depth_texture@fbo-depth-gl-depth-component32-blit

Tested with mtt-piglit on hw 8,9,10,11,13 and mtt-glretrace on windows and linux.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-09-05 11:22:42 -06:00
Neha Bhende
53091a0312 svga: convert dst format to linear when blending is enabled.
When blending is enabled, framebuffer colorspace has to be linear.
Previously, we never hit this case because we were not supporting sRGB
drawable. Previous patch added that support.

Tested with mtt glretrace, viewperf, piglit, conform.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-09-05 11:22:42 -06:00
Neha Bhende
dfab1289e8 winsys/svga: Avoid cap2 code path for now
CAP2 functionality is not yet part of vmwgfx. This is causing unnecessary
dmesg error messages.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-09-05 11:22:42 -06:00
Neha Bhende
8449c33a27 svga: start using SVGA3dCmdIntraSurfaceCopy command for svga_blit.
Basically, SVGA3dCmdIntraSurfaceCopy command allow copying when
source and destination are same.

Tested with MTT piglit, glretrace, viewperf, conform

v2: changes as per Charmaine's comment
v3: changes as per Charmaine's comment

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-05 11:22:42 -06:00
Neha Bhende
4639ef3763 svga/winsys: Add cap2 support in winsys
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-05 11:22:42 -06:00
Neha Bhende
6b3627da08 svga: Add SVGA3dCmdIntraSurfaceCopy command support in OpenGL driver
v2: changes as per Charmaine's comment

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-09-05 11:22:42 -06:00
Brian Paul
bac94dfefa svga: update device header files from upstream
This is a squash commit of several earlier patches.

Signed-off-by: Brian Paul <brianp@vmware.com>
2018-09-05 11:22:42 -06:00
Charmaine Lee
f4f39fa5d9 winsys/drm: Fix assert when try to accumulate an invalid fd
This patch makes sure there is a valid fd before merging it
to the context's fd in vmw_svga_winsys_fence_server_sync().

This fixes the assert running webot.
No regression running kmscube.

Reviewed-by: Sinclair Yeh <syeh@vmware.com>
2018-09-05 11:22:42 -06:00
Eric Anholt
16f17e3a3c loader: Drop unused argument from dri3_update_drawable().
The argument has never been used since the function was added.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2018-09-05 10:11:27 -07:00
Alejandro Piñeiro
4e1f8d82c2 i965/fs: include multisamplers on image_intrinsic_coord_components
This is the second patch needed to fix the following piglit tests:

   tests/spec/arb_gl_spirv/linker/uniform/multisampler.shader_test
   tests/spec/arb_gl_spirv/linker/uniform/multisampler-array.shader_test

Although in this case it doesn't affect so many borrowed tests, as
there aren't too many tests using multisamplers on Intel.

It is worth to note that this patch is also needed when those tests
are run on GLSL mode (using the --glsl option). Although most Intel
drivers would not be able to run/execute tests using multisamplers, as
GL_MAX_IMAGE_SAMPLES is zero, technically those tests are expected to
link correctly, so linking tests should pass.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-05 17:02:28 +02:00
Alejandro Piñeiro
8969777686 i965: move brw_nir_lower_gl_images call
At this moment that lowering is using info coming from the
UniformStorage, so for the ARB_gl_spirv codepath, it needs to be done
after calling gl_nir_link_uniforms. As for the GLSL codepath it can
also be called later, we just move the call on both cases, to avoid
adding several shader->spirv_data checks, and keep the patch as small
as possible.

This is the first patch needed to fix the following piglit tests:

  tests/spec/arb_gl_spirv/linker/uniform/multisampler.shader_test
  tests/spec/arb_gl_spirv/linker/uniform/multisampler-array.shader_test

but fixes thousands of tests when borrowing the tests from other specs
(that needs to be done manually right now).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-05 17:02:28 +02:00
Alejandro Piñeiro
2a6182fe06 intel/compiler: rename brw_nir_lower_glsl_images
To brw_nir_lower_gl_images, as it will be also used on the
ARB_gl_spirv codepath, that doesn't involves GLSL at all. So the
lowering is about images following the OpenGL semantics. In any case
"brw_nir_lower_opengl_images" seemed too long to me, so I just used
gl. That shortening is already used on other parts of the code.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-05 17:02:28 +02:00
Alejandro Piñeiro
960f6459be intel/compiler: remove unused variable num_images
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-05 17:02:28 +02:00
Gert Wollny
218ff0d510 winsys/virgl/vtest: Correct off-by-one error in resource allocation
The resource bo array must already extended when the target index is
equal to the current size of the array.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
2018-09-05 13:54:01 +02:00
Gert Wollny
5341260f62 winsys/virgl: Initialize value to silence valgrind
Silences:

  Conditional jump or move depends on uninitialised value(s)
  at 0xB72F2C0: virgl_drm_winsys_create (virgl_drm_winsys.c:854)
  by 0xB72F2C0: virgl_drm_screen_create (virgl_drm_winsys.c:926)
  by 0xB21C885: pipe_virgl_create_screen (drm_helper.h:275)
  by 0xB7201F0: pipe_loader_create_screen (pipe_loader.c:137)
  by 0xB639C91: dri2_init_screen (dri2.c:2112)
  by 0xB634F68: driCreateNewScreen2 (dri_util.c:153)
  by 0x63023E6: dri3_create_screen (dri3_glx.c:893)
  by 0x62D35BD: AllocAndFetchScreenConfigs (glxext.c:820)
  by 0x62D35BD: __glXInitialize (glxext.c:946)
  by 0x62CECB3: GetGLXPrivScreenConfig (glxcmds.c:174)
  by 0x62CF69C: glXQueryExtensionsString (glxcmds.c:1304)
  by 0x60AA7D9: ??? (in /usr/lib/x86_64-linux-gnu/libwaffle-1.so.0.5.2)
  by 0x4F81450: wfl_checked_display_connect (piglit-util-waffle.h:74)
  by 0x4F829E0: piglit_wfl_framework_init (piglit_wfl_framework.c:627)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
2018-09-05 13:54:01 +02:00
Gert Wollny
9b0e8d8723 winsys/virgl: correct resource and handle allocation (v2)
Fixes crash with
  piglit/bin/map_buffer_range-invalidate CopyBufferSubData \
                               increment-offset -auto -fbo

* Resize the resource storage already when the count is equal to the
  allocated size, fixes:

  Invalid write of size 8
  at 0xB72E4CF: virgl_drm_add_res (virgl_drm_winsys.c:629)
  by 0xB72E4CF: virgl_drm_emit_res (virgl_drm_winsys.c:663)
  by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776)
  by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585)
  by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940)
  by 0x109A1E: upload (invalidate.c:169)
  by 0x109C2F: piglit_display (invalidate.c:215)
  by 0x4F80FBE: run_test (piglit_fbo_framework.c:52)
  by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229)
  by 0x10949D: main (invalidate.c:47)
  Address 0xbe07d30 is 0 bytes after a block of size 4,096 alloc'd
  at 0x4C31B25: calloc (in
       /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so)
  by 0xB72DAAF: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:567)

* Also resize the space allocated for the handles, fixes:

  Invalid write of size 4
  at 0xB72E4F0: virgl_drm_add_res (virgl_drm_winsys.c:631)
  by 0xB72E4F0: virgl_drm_emit_res (virgl_drm_winsys.c:663)
  by 0xB72A44A: virgl_encode_resource_copy_region (virgl_encode.c:776)
  by 0xB40CD12: st_copy_buffer_subdata (st_cb_bufferobjects.c:585)
  by 0xB244A3B: _mesa_CopyBufferSubData (bufferobj.c:2940)
  by 0x109A1E: upload (invalidate.c:169)
  by 0x109C2F: piglit_display (invalidate.c:215)
  by 0x4F80FBE: run_test (piglit_fbo_framework.c:52)
  by 0x4F66E5F: piglit_gl_test_run (piglit-framework-gl.c:229)
  by 0x10949D: main (invalidate.c:47)
  Address 0xbe08570 is 0 bytes after a block of size 2,048 alloc'd
  at 0x4C2FB0F: malloc (
    in /usr/lib/valgrind/vgpreload_memcheck-amd64- linux.so)
  by 0xB72DAC8: virgl_drm_cmd_buf_create (virgl_drm_winsys.c:572)

Fixes: 4b15b5e803 ("virgl: resize resource bo allocation if we need to.")

v2: - Use REALLOC macro and avoid memory leak when re-allocation fails
    - add Fixes tag (both Emil Velikov)
    - reorder commit message

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
2018-09-05 13:54:01 +02:00
Tomeu Vizoso
f13de57edb virgl: use hw-atomics instead of in-ssbo ones
Emulating atomics on top of ssbos can lead to too small max SSBO count,
so let's use the hw-atomics mechanism to expose atomic buffers instead.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:58 +01:00
Erik Faye-Lund
1bd927d997 virgl: update minor differences to upstream header
virgl_protocol.h is considered to have it's upstream in the
virglrenderer repository, and somehow these minor differences has
crept in.

Let's sync with the upstream to avoid this.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:52 +01:00
Erik Faye-Lund
5a587d18d5 gallium: add PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER{S,_BUFFERS}
This moves the evergreen-specific max-sizes out as a driver-cap, so
other drivers with less strict requirements also can use hw-atomics.

Remove ssbo_atomic as it's no longer needed.

We should now be able to use hw-atomics for some stages and not for
other, if needed.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:46 +01:00
Erik Faye-Lund
d641d3f48b gallium: add PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS
This gets rid of a r600 specific hack in the state-tracker, and prepares
for other drivers to be able to use hw-atomics.

While we're at it, clean up some indentation in the various drivers.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:37 +01:00
Erik Faye-Lund
84795f8c64 st/mesa: simplify MaxAtomicBufferSize-logic
MaxAtomicCounters has already been assigned in the loop above in the
ssbo_atomic = true case, so this will calculate the same value as the
default.

While we're at it, fixup indentation on the MaxAtomicBufferBindings
assign.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:33 +01:00
Erik Faye-Lund
38f0c078de st/mesa: clean up atomic vs ssbo code
This makes the code a bit easier to follow; we first set up
MaxShaderStorageBlocks, then we either set up a dedicated
MaxAtomicBuffers, or we split MaxShaderStorageBlocks in two.

While we're at it, also make the SSBO-splitting code tolerate the
hypothetical case of having an odd number of SSBOs without incorrectly
dropping the last SSBO.

This has the nice result that the SSBOs and atomic buffers are dealt
with almost completely orthogonally, easing some upcoming patches.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:27 +01:00
Erik Faye-Lund
a805e4e9de st/mesa: use real bool for can_ubo
We're doing full c99 now, so there's no point in using the old boolean
type.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2018-09-05 05:46:09 +01:00
Marek Olšák
28e542dcdb gallium/u_threaded: increase batch size to increase performance
This reduces mutex overhead.

radeonsi: +4.4% performance with piglit/drawoverhead, DrawElements, Ryzen X1700
iris_dri.so: +14% with piglit/drawoverhead, DrawArrays, i7 7700HQ.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-09-04 14:31:56 -04:00
Marek Olšák
ebd5806e0f st/vdpau: silence an unitialized-variable warning 2018-09-04 14:01:43 -04:00
Marek Olšák
725e8ad559 st/mesa: help fix stencil border color for GL_DEPTH_STENCIL textures
GL_STENCIL_INDEX uses GL_INTENSITY for the border color, which is nicer
to hardware that doesn't read the stencil border value from the X channel.

This fixes a bunch of dEQP tests on Vega & Raven.

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
2018-09-04 14:01:43 -04:00
Ernestas Kulik
d49904085a glsl_to_tgsi: Fix potential leak
Reported by Coverity: arr_live_ranges is freed in a different branch
than the one in which it was allocated.

Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2018-09-04 14:01:43 -04:00
Ernestas Kulik
ea1e50cc16 u_vbuf: Fix leak
Reported by Coverity: data is heap-allocated, but only freed in the
info->index_size != 0 branch.

Signed-off-by: Ernestas Kulik <ernestas.kulik@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Cc: 18.2 <mesa-stable@lists.freedesktop.org>
2018-09-04 14:01:43 -04:00
Eric Anholt
2e59b88903 freedreno: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.

v2: Rebase on new gallium caps

Reviewed-by: Rob Clark <robdclark@gmail.com> (v1)
2018-09-04 08:08:22 -07:00
Eric Anholt
492b74b445 v3d: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.

v2: Rebase on new gallium caps
2018-09-04 08:08:18 -07:00
Eric Anholt
c311e00000 vc4: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.

v2: drop GLSL level in favor of defaults.
v3: Rebase on new gallium caps
2018-09-04 08:08:10 -07:00
Eric Anholt
ad782a7020 gallium: Add a helper for implementing PIPE_CAP_* default values.
One of the pains of implementing a gallium driver is filling in a million
pipe caps you don't know about yet when you're just starting out.  One of
the pains of working on gallium is copy-and-pasting your new PIPE_CAP into
each driver.  We can fix both of these by having each driver call into the
default helper from their default case, so that both sides can ignore each
other until they need to.

v2: fix i915g build, revert swr change to avoid breaking scons build
    (https://travis-ci.org/anholt/mesa/jobs/419739857)
v3: Rebase on 3 new gallium caps.

Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v1)
Cc: Bruce Cherniak <bruce.cherniak@intel.com>
Cc: George Kyriazis <george.kyriazis@intel.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
2018-09-04 08:07:52 -07:00
Jason Ekstrand
67571ae796 intel/compiler: Remove redundant nir_remove_dead_variables call
As of 07a2098a70, brw_nir_optimize calls nir_remove_dead_variables as
the last optimization.  Doing it again is just pointless.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-09-04 09:03:16 -05:00
Lionel Landwerlin
07a2098a70 intel: compiler: remove dead local variables at optimization pass
We're hitting an assert in gfxbench because one of the local variable
is a sampler (according to Jason this isn't valid) :

testfw_app: ../src/compiler/nir_types.cpp:551: void glsl_get_natural_size_align_bytes(const glsl_type*, unsigned int*, unsigned int*): Assertion `!"type does not have a natural size"' failed.

Since this particular variable isn't used, it can be eliminated by
removing unused local variables at the end of the optimization loop.
This makes sense also for valid local variables.

v2: Move additional local variable removal out of optimization loop,
    but before large constant removal (Jason/Lionel)

v3: Move the removal at the end of brw_nir_optimize()

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107806
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-09-03 17:24:19 +01:00
Andrii Simiklit
095600dad6 intel/decoder: fix the possible out of bounds group_iter
The "gen_group_get_length" function can return a negative value
and it can lead to the out of bounds group_iter.

v2: printing of "unknown command type" was added
v3: just the asserts are added

Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-09-03 11:14:30 +01:00
Bas Nieuwenhuizen
233718a199 radv: Fix CMASK dimensions.
Mirrors

1e40f69483 "ac/surface: fix CMASK fast clear for NPOT textures with mipmapping on SI/CI/VI"

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-03 09:24:30 +02:00
Bas Nieuwenhuizen
ab64891f4c radv: Use a lower max offchip buffer count.
No clue what gets fixed by this but both radeonsi and amdvlk do it.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-03 09:24:30 +02:00
Bas Nieuwenhuizen
4dc244eb44 radv: Add VEGA20 support.
Just mirror the radeonsi bits. Since this is just adding the extra
switch entries for new HW I think this should be fine for stable.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-09-03 09:24:30 +02:00
Dave Airlie
c1ba33c34b radv: don't expose linear depth surfaces on SI/CIK/VI either.
ac_surface.c: gfx6_compute_surface says
/* DB doesn't support linear layouts. */

Now if we expose linear depth and create a linear depth image
and use CmdCopyImage to copy into it, we can't map the underlying
memory and read it linearly which I think should work.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-09-03 11:38:00 +10:00
Mauro Rossi
ac0856ae41 egl/android: do not indent HAVE_DRM_GRALLOC preprocessor directive
Fixes: 3f7bca44d9 ("egl/android: #ifdef out flink name support")
Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
2018-09-02 11:27:08 +02:00
Jason Ekstrand
2ad9917e18 anv/blorp: Fix a comment as per Nanley's review feedback
This accidentally didn't make it into 62378c5e9e
2018-09-01 09:12:08 -05:00
Jason Ekstrand
62378c5e9e anv/blorp: Do more flushing around HiZ clears
We make the flush after a HiZ clear unconditional and add a flush/stall
before the clear as well.

Cc: mesa-stable@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107760
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
2018-09-01 09:08:36 -05:00
Ian Romanick
82530ce1b5 i965/vec4: Clamp indirect tes input array reads with 0x0fffffff
Page 190 of "Volume 7: 3D Media GPGPU Engine (Haswell)" says the valid
range of the offset is [0, 0FFFFFFFh].

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-09-01 00:23:45 -07:00
Ian Romanick
75666605c9 i965/vec4: Correctly handle uniform sources in generate_tes_add_indirect_urb_offset
Fixes failure in the new piglit test
tes-patch-input-array-vec2-index-invalid-rd.shader_test.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
2018-09-01 00:23:43 -07:00
Andres Gomez
adad7e3aa8 docs: update calendar to extended the 18.1 cycle by one more release
Due to having 2 additional RCs for 18.2.

Cc: Dylan Baker <dylan.c.baker@intel.com>
Cc: Juan A. Suarez <jasuarez@igalia.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
2018-09-01 02:23:14 +03:00