Commit graph

51424 commits

Author SHA1 Message Date
Eric Anholt
6882381a2e mesa: Require current libxcb.
Without that, people with buggy apps that looked at just the server
string for GLX_ARB_create_context would call this function that just
threw an error when you tried to make a context.  Google shows plenty
of complaints about this.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 12:29:12 -07:00
Tom Stellard
f92873be2c radeon/llvm: Don't use lp_build_swizzle_aos() for swizzles
This function assumes that lp_build_context::type is a vector type,
which is not true for r600 or radeonsi.

This fixes an assertion failure using glamor 2D accel.
2012-07-12 13:53:22 -04:00
Tom Stellard
185fc9a5ef radeonsi: Dump TGSI code prior to doing TGSI->LLVM conversion.
This way if the conversion fails, we know what the TGSI shader looks
like.
2012-07-12 13:53:22 -04:00
Kenneth Graunke
b546aebae9 i965: Delete previous workaround for textureGrad with shadow samplers.
It had many problems:
- The shadow comparison was done post-filtering.
- It required state-dependent recompiles whenever the comparison
  function changed.
- It didn't even work: many cases hit assertion failures.
- I never implemented it for the VS.

The new lowering pass which converts textureGrad to textureLod by
computing the LOD value works much better.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-12 10:20:26 -07:00
Kenneth Graunke
b0c8d3be73 i965: Add a lowering pass to convert TXD to TXL by computing the LOD.
Intel hardware doesn't natively support textureGrad with shadow
comparisons.  So we need to generate code to handle it somehow.

Based on the equations of page 205 of the OpenGL 3.0 specification,
it's possible to compute the LOD value that would be selected given the
gradient values.  Then, we can simply convert the TXD to a TXL.

Currently, this passes 34/46 of oglconform's shadow-grad subtests;
four cubemap tests are regressed.  We should investigate this in the
future.

v2: Apply abs() to the scalar case (thanks to Eric).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-12 10:20:23 -07:00
Kenneth Graunke
d9da350a83 glsl/ir_builder: Add a new swizzle_for_size() function.
This swizzles away unwanted components, while preserving the order of
the ones that remain.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-12 10:20:20 -07:00
Kenneth Graunke
0bb3d4ba54 glsl/ir_builder: Add a generic constructor for unary expressions.
I needed to compute logs and square roots in a patch I was working on,
and wanted to use the convenient interface.  We already have a similar
constructor for binops; adding one for unops seems reasonable.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-12 10:20:18 -07:00
Kenneth Graunke
b656df990f glsl: Initialize coordinate to NULL in ir_texture constructor.
I ran into this while trying to create a TXS query, which doesn't have a
coordinate.  Since it didn't get initialized to NULL, a bunch of
visitors tried to access it and crashed.

Most of the time, this won't be a problem, but it's just a good idea.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2012-07-12 10:19:38 -07:00
José Fonseca
d9a8cd76e5 st/xorg: Fix build failure due to symbol clash. 2012-07-12 16:02:49 +01:00
Marek Olšák
0f3659bb56 docs: update relnotes-8.1 and GL3 status 2012-07-12 13:05:59 +02:00
Marek Olšák
63d8c8baa9 st/mesa: expose new transform feedback extensions 2012-07-12 13:05:59 +02:00
Marek Olšák
d24ece97e5 mesa: add ARB_transform_feedback_instanced extension enable flag
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:59 +02:00
Marek Olšák
db7404defd mesa: implement new DrawTransformFeedback functions
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:59 +02:00
Marek Olšák
7e0cb473b0 mesa: implement display list support for new DrawTransformFeedback functions
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:59 +02:00
Marek Olšák
ce16ca4635 mesa: implement display list support for indexed query functions
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:59 +02:00
Marek Olšák
553e13dbc2 mesa: implement indexed query functions from ARB_transform_feedback3
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:58 +02:00
Marek Olšák
375e73d859 mesa: implement glGet queries and error handling for ARB_transform_feedback3
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:58 +02:00
Marek Olšák
21cb5ed20d glsl: implement ARB_transform_feedback3 in the linker
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:58 +02:00
Marek Olšák
9576d555e0 glapi: add ARB_transform_feedback_instanced
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:58 +02:00
Marek Olšák
6d13d91f4e glapi: add ARB_transform_feedback3
Acked-by: Ian Romanick <ian.d.romanick@intel.com>
2012-07-12 13:05:58 +02:00
Marek Olšák
e773a48a3b r600g: fix uploading non-zero mipmap levels of depth textures
This fixes piglit/depth-level-clamp.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
fe1fd67556 r600g: don't flush depth textures set as colorbuffers
The only case a depth buffer can be set as a color buffer is when flushing.

That wasn't always the case, but now this code isn't required anymore.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
6842d5fced r600g: don't set dirty_db_mask for a flushed depth texture
A flush depth texture is never set as a depth buffer and never flushed.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
5a17d8318e r600g: flush depth textures bound to vertex shaders
This was missing/broken. There are also minor code cleanups.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:31 +02:00
Marek Olšák
dee58f94af r600g: do fine-grained depth texture flushing
- maintain a mask of which mipmap levels are dirty (instead of one big flag)
- only flush what was requested at a given point and not the whole resource
  (most often only one level and one layer has to be flushed)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
df79eb5956 r600g: remove is_flush from DSA state
we can just update the state when decompressing, there's no need to add
additional info into the DSA state

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
43e3f19c76 r600g: set DISABLE in CB_COLOR_CONTROL if colormask is 0
this will be useful for in-place DB decompression, otherwise should be harmless

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
4fe74412cf r600g: move CB_SHADER_MASK setup into cb_misc_state
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
a1a1ff5ec0 r600g: move MULTIWRITE setup into cb_misc_state for r6xx-r7xx
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
0ea76916e6 r600g: move CB_TARGET_MASK setup into new cb_misc_state
to remove some overhead from draw_vbo. This is a derived state.

BTW, I've got no idea how compute interacts with 3D here, but it should
use cb_misc_state, so that 3D and compute don't conflict.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
5ba15d8d38 st/mesa: implement accelerated stencil blitting using shader stencil export
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
a7f3697eb8 st/mesa: set colormask to zero when blitting depth
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
5a74e17ab0 gallium/u_blit: remove useless memset calls
the structure is calloc'd.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
24e0a26335 gallium/u_blit: drop not-very-useful wrapper around util_blit_pixels_writemask
just rename it to util_blit_pixels

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
3f13b5da15 gallium/u_blit: don't do two copies for non-2D textures
Because u_blit couldn't sample a 1D, 3D, CUBE and ARRAY texture, we created
a 2D texture holding a copy of one slice of the source texture (even for 1D).

Let's just do it right.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
2dca61bcb3 gallium/util: move pipe_tex_to_tgsi_tex helper function into u_inlines
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
bdaf0a085b gallium/u_blitter: accelerate stencil-only copying
This doesn't seem to be used by anything yet, but better safe than sorry.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
12fd81f9e7 gallium/u_blitter: accelerate depth-stencil copying using shader stencil export
This fixes stencil buffer write transfers on r600g.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
76db2c121c gallium: add util_format_stencil_only helper function
used for stencil sampler views.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
a730838a42 gallium/u_blitter: minify depth0 when initializing last_layer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
91cf9fe988 gallium/u_gen_mipmap: accelerate depth texture mipmap generation
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Marek Olšák
13b0af721a mesa: remove assertions that do not allow compressed 2D_ARRAY textures
NOTE: This is a candidate for the 8.0 branch.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-07-12 02:08:30 +02:00
Paul Berry
33202b4876 i965/msaa: Enable CMS layout on Gen7 for the formats that support it.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:50 -07:00
Paul Berry
4ebbc76621 i965/msaa: Add CMS support to blorp.
This patch updates the blorp engine to properly handle the case where
the surface being textured from uses Gen7's CMS MSAA layout.  The
following changes were necessary:

- Before reading color values from the surface, we need to read from
  the MCS buffer using the ld_mcs sampler message.  This is done by
  the mcs_fetch() function, and the result is stored in the mcs_data
  register.  This only needs to be done once per pixel, since the MCS
  value is shared between all samples belonging to a pixel.

- When reading color values from the surface, we need to use the
  ld2dms sampler message instead of the ld2dss message, and we need to
  provide the value read from the MCS buffer as an argument.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
754953693d i965/msaa: Add CMS-related sampler messages to brw_defines.h.
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
7b3263af69 i965/msaa: Set SURFACE_STATE properly when CMS MSAA is in use.
When a buffer using Gen7's CMS MSAA layout is bound to a texture or a
render target, the SURFACE_STATE structure needs to point to the MCS
buffer and to indicate its pitch.  This patch updates the functions
that emit SURFACE_STATE to handle CMS layout properly.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
0ba813506d i965/msaa: Add CMS MSAA settings to brw_structs.h.
Previously the DWORD used to control the CMS MSAA layout was just a
pad value, because we didn't use it.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
ccae1b1cd7 i965/msaa: Allocate MCS buffer when CMS MSAA is in use.
To implement Gen7's CMS MSAA layout, we need an extra buffer, the MCS
(Multisample Control Surface) buffer.  This patch introduces code for
allocating and deallocating the buffer, and storing a pointer to it in
the intel_mipmap_tree struct.

No functional change, since the CMS layout is not enabled yet.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
1bd4d456cd i965/msaa: Add an enum to describe MSAA layout.
From the Ivy Bridge PRM, Vol 1 Part 1, p112:

    There are three types of multisampled surface layouts designated
    as follows:
      - IMS Interleaved Multisampled Surface
      - CMS Compressed Mulitsampled Surface
      - UMS Uncompressed Multisampled Surface

Previously, the i965 driver only used IMS and UMS formats, and
distinguished beetween them using the boolean
intel_mipmap_tree::msaa_is_interleaved.  To facilitate adding support
for the CMS format, this patch replaces that boolean (and other
booleans derived from it) with an enum
INTEL_MSAA_LAYOUT_{IMS,CMS,UMS}.  It also updates the terminology used
in comments throughout the driver to match the IMS/CMS/UMS terminology
used in the PRM.  CMS layout is not yet used.

The enum has a fourth possible value, INTEL_MSAA_LAYOUT_NONE, which is
used for non-multisampled surfaces.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00
Paul Berry
67b0f7c7dd i965/msaa: Move {rt,tex}_interleaved into blorp program key.
On Gen6, MSAA buffers always use an interleaved layout and non-MSAA
buffers always use a non-interleaved layout, so it is not strictly
necessary to keep track of the layout of the texture and render target
surfaces in the blorp program key.  However, it is cleaner to do so,
since (a) it makes the blorp compiler less dependent on implicit
knowledge about how the GPU pipeline is configured, and (b) it paves
the way for implementing compressed multisampled surfaces in Gen7.

This patch won't cause any redundant compiles, because the layout of
the texture and render target surfaces depends on other parameters
that are already in the blorp program key.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2012-07-11 15:14:49 -07:00