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Author SHA1 Message Date
David Heidelberg
68215332a8 build: pass licensing information in SPDX form 
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@igalia.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29972>
 2024-06-29 12:42:49 -07:00
Samuel Pitoiset
cc48e12431 radv: suspend user conditional rendering when DGC has task shaders 
Otherwise the DGC ACE IB would be uninitialized and it would hang.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29954>
 2024-06-28 14:35:22 +00:00
Konstantin Seurer
9ae1c5dce3 radv: Refactor radv_(dst|src)_access_flush 
A few ifs should be faster and more readable than looping over every set
bit.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
41619da397 radv: Handle AS access bits like shader storage access bits 
Acceleration structures are accessed directly from shaders or via
PKT3_WRITE_DATA.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
ca96abe1cb radv: Remove write access handling from radv_dst_access_flush 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
3eefd0b040 radv: Remove handling for expanded access flags 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
135348a3c3 radv: Remove no-op access flag handling 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Konstantin Seurer
3acab3dfff radv: Use vk_expand_(src|dst)_access_flags2 
Simplifies access flags handling since the driver doesn't have to worry
about VK_ACCESS_2_MEMORY_READ_BIT and friends.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29051>
 2024-06-28 10:41:49 +00:00
Samuel Pitoiset
88864b707a radv: enable task shaders support with NV DGC 
No games are using task shaders with DGC at the moment but this is
supposed to work.

This fixes test_amplification_shader_execute_indirect from vkd3d.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
e6aee84265 radv: fix a synchronization issue with non-preprocessed DGC with task shader 
We need to make sure that the DGC ACE IB will wait for the DGC
prepare shader before the execution starts. When DGC is preprocessed
the synchronization is already correct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
74713469e1 radv: disable conditional rendering with DGC and task shaders 
When the DGC prepare shader is conditionally executed on the graphics
queue, the generated IBs might be uninitialized. It's fine for the
DGC GFX IB because the INDIRECT_PACKET would also be conditionally
skipped but it's not possible to do that for the DGC ACE IB
(ie. no IB2 on compute).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
fec2385301 radv: emit push constant for task shaders with DGC 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
1ffb420edd radv: adjust the base upload offset when DGC uses task shaders 
The upload space is after the DGC ACE IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
f55d4f2f09 radv: reserve space for push constants in the DGC ACE IB 
The upload space will be shared for both IBs when push constants need
to be allocated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
8d321421c7 radv: rework emitting push constants with DGC 
Using a push constant stages mask to emit them in the DGC ACE IB for
task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
f6150edbb3 radv: split allocating and emitting push constants with DGC 
This will allow us to emit push constants for task shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
1f7bdcfa8d radv: add a helper that determines if DGC uses task shaders 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
58327fd3bf radv: pre-compute the base upload offset in radv_prepare_dgc() 
It will need to be adjusted if task+mesh shaders need to allocate
push constants.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
842f3ea133 radv: improve clarity of DGC offset computations 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
 2024-06-28 06:19:56 +00:00
Samuel Pitoiset
bc52e77397 radv: fix incorrect cache flushes before decompressing DCC on compute 
Found by luck.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29940>
 2024-06-28 05:54:20 +00:00
Samuel Pitoiset
037eaa962b radv: add support for executing the DGC ACE IB 
It's disabled for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:50 +00:00
Samuel Pitoiset
1e0c6fab21 radv: add support for preparing the ACE IB in DGC 
This is still missing push constants.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:50 +00:00
Samuel Pitoiset
723acbe1e2 radv: add a helper to pad DGC IB 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:50 +00:00
Samuel Pitoiset
0a5c6415d1 radv: refactor some DGC helpers in preparation for the ACE IB 
These will be re-used for generating the ACE IB.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:49 +00:00
Samuel Pitoiset
12cc97a157 radv: prepare for DISPATCH_TASKMESH_DIRECT_ACE emission in the DGC shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:49 +00:00
Samuel Pitoiset
8a81a6066d radv: prepare for DISPATCH_TASKMESH_GFX emission in the DGC shader 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:49 +00:00
Samuel Pitoiset
bdbe3e5886 radv: add support for computing the DGC ACE IB size 
For task shaders, RADV will need to prepare two command buffers in the
DGC prepare shader. The preprocess buffer will be splitted in two
parts, one for GFX and one for ACE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:49 +00:00
Samuel Pitoiset
99cd8b6a54 radv: add a helper to execute a DGC IB 
It will be used to execute DGC IB for task shaders too.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29814>
 2024-06-27 10:22:49 +00:00
Jeremy Gebben
da1a7c04bc radv: Return hang status from radv_check_gpu_hangs() 
Return VK_ERROR_DEVICE_LOST if a hang is detected. This is necessary
because the application needs to know if it should call
vkGetDeviceFaultInfoEXT().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29921>
 2024-06-27 06:07:53 +00:00
Alyssa Rosenzweig
dd85b50d18 treewide: use nir_break_if 
Via Coccinelle patch and some manual hunk editing:

    @@
    expression b, E;
    @@

    -nir_push_if(b, E);
    -{
    -nir_jump(b, nir_jump_break);
    -}
    -nir_pop_if(b, NULL);
    +nir_break_if(b, E);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29877>
 2024-06-26 19:07:35 +00:00
Samuel Pitoiset
fec9b56f17 radv/amdgpu: fix chaining CS with external IBs on compute queue 
In a scenario where two non-concurrent cmdbufs are submitted to the
compute queue and with the second one using DGCC, the driver would have
chained the CS of the first cmdbuf to the new IB created right after
the DGC IB is executed.

Found while working on DGC task shader with vkd3d-proton.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29913>
 2024-06-26 17:03:10 +00:00
Samuel Pitoiset
4db32ac7ef radv/amdgpu: use the non-IB path for dumping CS with external IBs 
Only the first CS chunk was dumped, but this allows to dump CS that
are post the DGC execute IB when on compute queue.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29832>
 2024-06-25 07:24:50 +00:00
Samuel Pitoiset
030d6e6280 radv/amdgpu: allow cs_execute_ib() to pass a VA instead of a BO 
DGC IBs are considered external IBs because they aren't managed by
the winsys and the BO itself isn't really useful. Passing a VA instead
will help for future work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29600>
 2024-06-24 08:02:07 +00:00
Samuel Pitoiset
e51ae61a4d radv: add the DGC preprocess BO to the cmdbuf BO list 
This wasn't needed in practice because DGC NV is only enabled for
vkd3d-proton and it always uses the global BO list but better to add it
anyways.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29600>
 2024-06-24 08:02:07 +00:00
Samuel Pitoiset
25bf3200e2 radv: remove useless draw_id to radv_emit_userdata_task() 
It's always 0 for direct draws.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29830>
 2024-06-24 06:38:43 +00:00
Samuel Pitoiset
d2b1d38392 radv: remove useless masking in radv_cs_emit_indirect_mesh_draw_packet() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29830>
 2024-06-24 06:38:43 +00:00
Samuel Pitoiset
b2ff08800e radv: remove dead mesh shader code for indirect draws 
This path is never used by mesh shaders.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29830>
 2024-06-24 06:38:43 +00:00
Samuel Pitoiset
d922a0e875 radv: use radv_shader_info::user_data_0 for task shaders 
To avoid duplicating the base user SGPR.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29830>
 2024-06-24 06:38:43 +00:00
Samuel Pitoiset
334046648b radv: cleanup getting AC_UD_TASK_RING_ENTRY for mesh shader 
The last VGT shader is the mesh shader.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29830>
 2024-06-24 06:38:43 +00:00
Konstantin Seurer
ee751a26fc radv/rra: Enable RADV_RRA_TRACE_COPY_AFTER_BUILD by default 
RADV_RRA_TRACE_COPY_AFTER_BUILD is more accurate and the memory issues
are fixed now.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
aa1b9d9be5 radv/rra: Rework calculating the ray history size 
The previous approach was broken when writing empty metadata.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
090ca37352 radv/rra: Reduce the memory requirement of copy_after_build 
vkd3d-proton always sets the acceleration structure size to be the
whole buffer size. Because of that, allocating read back buffers
for all acceleration structures causes a system with a finite amount
of RAM to OOM.

This is solved by allocating read back buffers on build where the
required size is known.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
c2c555402b radv/rra: Bump rt_driver_interface_version to 8.0 
8.0 matches the layout we emit more closely.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
55f1fe9bc3 radv/rra: Fix reporting the isec invocations 
Copy+paste mistake, we always set the last call to accept.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
97c0f264f0 radv/rra: Fix disabling the ray history 
There are a bunch of NULL pointer dereferences that went unnoticed
because the feature is enabled by default.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
bd377cfe89 radv/rra: Move some code into handle_accel_struct_write 
The code is the same for all callers.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Konstantin Seurer
ea69f7bc89 radv/rra: Detect BVHs with back edges 
Avoid overflowing the stack and fail validation.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29537>
 2024-06-21 17:47:53 +00:00
Alyssa Rosenzweig
da752ed7c1 treewide: use nir_def_replace sometimes 
Two Coccinelle patches here. Didn't catch nearly as much as I would've liked but
it's a start.

Coccinelle patch:

    @@
    expression intr, repl;
    @@

    -nir_def_rewrite_uses(&intr->def, repl);
    -nir_instr_remove(&intr->instr);
    +nir_def_replace(&intr->def, repl);

Coccinelle patch:

    @@
    identifier intr;
    expression instr, repl;
    @@

    nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
    ...
    -nir_def_rewrite_uses(&intr->def, repl);
    -nir_instr_remove(instr);
    +nir_def_replace(&intr->def, repl);

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com> [broadcom]
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com> [lima]
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> [etna]
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com> [r300]
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29817>
 2024-06-21 15:36:56 +00:00
Konstantin Seurer
23ee6ca801 radv/meta: Use READ access for dst_access_flush 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29780>
 2024-06-21 12:52:39 +00:00
Konstantin Seurer
14f7b077c8 radv: Remove dead access bits 
READ access bits are dead as radv_src_access_flush arguments and WRITE
access bits are dead as radv_dst_access_flush arguments.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29780>
 2024-06-21 12:52:39 +00:00