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radv: disable conditional rendering with DGC and task shaders

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When the DGC prepare shader is conditionally executed on the graphics
queue, the generated IBs might be uninitialized. It's fine for the
DGC GFX IB because the INDIRECT_PACKET would also be conditionally
skipped but it's not possible to do that for the DGC ACE IB
(ie. no IB2 on compute).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29935>
This commit is contained in:
Samuel Pitoiset 2024-06-27 12:07:36 +02:00 • committed by Marge Bot
parent fec2385301
commit 74713469e1
1 changed files with 5 additions and 2 deletions
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7
src/amd/vulkan/radv_device_generated_commands.c
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@ -2295,9 +2295,12 @@ radv_use_dgc_predication(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCo
/* Enable conditional rendering (if not enabled by user) to skip prepare/execute DGC calls when
* the indirect sequence count might be zero. This can only be enabled on GFX because on ACE it's
* not possible to skip the execute DGC call (ie. no INDIRECT_PACKET)
* not possible to skip the execute DGC call (ie. no INDIRECT_PACKET). It should also be disabled
* when the graphics pipelines has a task shader for the same reason (otherwise the DGC ACE IB
* would be uninitialized).
*/
return cmd_buffer->qf == RADV_QUEUE_GENERAL && seq_count_buffer && !cmd_buffer->state.predicating;
return cmd_buffer->qf == RADV_QUEUE_GENERAL && !radv_dgc_with_task_shader(pGeneratedCommandsInfo) &&
seq_count_buffer && !cmd_buffer->state.predicating;
}
static bool