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radv: fix incorrect cache flushes before decompressing DCC on compute

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Found by luck.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29940>
This commit is contained in:
Samuel Pitoiset 2024-06-27 15:02:00 +02:00 • committed by Marge Bot
parent edcad250ed
commit bc52e77397
1 changed files with 1 additions and 1 deletions
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2
src/amd/vulkan/meta/radv_meta_fast_clear.c
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@ -670,7 +670,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag
struct radv_image_view load_iview = {0};
struct radv_image_view store_iview = {0};
cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, image);
cmd_buffer->state.flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, image);
if (!device->meta_state.fast_clear_flush.cmask_eliminate_pipeline) {
VkResult ret = radv_device_init_meta_fast_clear_flush_state_internal(device);