Commit graph

213937 commits

Author SHA1 Message Date
Samuel Pitoiset
5cb400a97b amd,radv,radeonsi: add ac_emit_cp_inhibit_clockgating()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
2025-10-23 08:29:26 +00:00
Samuel Pitoiset
bc1080e27f amd,radv,radeonsi: add and use more ac_cmdbuf_XXX helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
2025-10-23 08:29:26 +00:00
Samuel Pitoiset
a4a834859e radv/amdgpu: remove now unused radeon_emit helpers
Keep radeon_emit_unchecked() for now because it's special.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
2025-10-23 08:29:25 +00:00
Samuel Pitoiset
0fb21e2299 amd,radv: add ac_emit_cp_indirect_buffer()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
2025-10-23 08:29:25 +00:00
Samuel Pitoiset
3efe8ec16b radv/amdgpu: use common emit helpers in radv_amdgpu_cs_chain_dgc_ib()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
2025-10-23 08:29:25 +00:00
Samuel Pitoiset
50ec03054c amd,radv,radeonsi: add ac_pm4_emit_commands()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37956>
2025-10-23 08:29:24 +00:00
Samuel Pitoiset
22cb7b5fe2 radv: bump image limit properties on GFX12
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14150
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
2025-10-23 07:56:39 +00:00
Samuel Pitoiset
002ebb4fe5 radv: configure the screen scissor to the maximum image dimension
The framebuffer dimension exposed to apps is still 16k but since the
driver allows 32k image on GFX12+, meta operations might perform
operations (like a copy) using graphics.

While we are at it, use the correct bitfield for setting BR_X/BR_Y on
GFX12.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
2025-10-23 07:56:38 +00:00
Samuel Pitoiset
bcde1a6650 radv: initialize image properties earlier
This is less error prone and it removes redundant code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
2025-10-23 07:56:37 +00:00
Samuel Pitoiset
3678437ca0 radv: bump maxImageDimension3D to 8192 on GFX10+
This was missing and it aligns to VkImageFormatProperties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
2025-10-23 07:56:36 +00:00
Samuel Pitoiset
5c71ffbc3d radv: bump maxImageArrayLayers to 8192 on GFX10+
This was missing and it aligns to VkImageFormatProperties.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
2025-10-23 07:56:36 +00:00
Konstantin Seurer
47ffe2ecd4 aco: Fixup out_launch_size_y in the RT prolog for 1D dispatch
launch_size_y is set to ACO_RT_CONVERTED_2D_LAUNCH_SIZE for 1D
dispatches. The prolog needs to set it to 1 so that the app shader
loads the correct value.

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37974>
2025-10-23 07:56:35 +00:00
Samuel Pitoiset
067b05d5b9 radv: remove radv_pipeline_layout::push_constant_size
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37769>
2025-10-23 07:25:41 +00:00
Samuel Pitoiset
d15b411262 radv: remove radv_shader_layout::push_constant_size
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37769>
2025-10-23 07:25:41 +00:00
Samuel Pitoiset
2985322ed1 radv: gather push constant size from shaders for pipelines
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37769>
2025-10-23 07:25:41 +00:00
Samuel Pitoiset
97dbf7b895 radv/rt: radv: gather push constant size from shaders for RT
And store the total push constant size to the RT prolog.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37769>
2025-10-23 07:25:41 +00:00
Samuel Pitoiset
aa44a5a4ae radv: gather push constant size from shaders for ESO
Instead of using the shader layout which won't exist anymore with heap.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37769>
2025-10-23 07:25:41 +00:00
Romaric Jodin
a25e88cd84 aux/trace: remove -I argument
enums2names.py is only uses in one place. I propose to remove the -I
argument that is not strictly necessary as we can already get the
header name from the `-H` argument.

That modification is motivated by the need to help ninja-to-soong to
generate proper rule for the Android build system.

ninja-to-soong can't differenciate output file location and a string
matching the output file name.

Ref #14072

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37785>
2025-10-23 07:03:01 +00:00
Faith Ekstrand
aa0f404f7b nvk: Disable sampleLocationsSampleCounts for 1x MSAA
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Suggested-by: Mel Henning <mhenning@darkrefraction.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14108
Fixes: a34edc7500 ("nvk: Fill out sample locations on Maxwell B+")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38018>
2025-10-22 21:55:22 +00:00
Faith Ekstrand
d1793c7a59 nvk: Include the chipset in the pipeline/binary cache UUID
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38018>
2025-10-22 21:55:22 +00:00
Lionel Landwerlin
aa929ea706 nir/lower_io: add missing levels intrinsics to get_io_index_src_number
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c7ac46a1d8 ("nir/lower_io: add get_io_index_src_number support for image intrinsics")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38012>
2025-10-22 21:21:47 +00:00
Aitor Camacho
cf49338ccd kk: Expose missing BC formats
Exposing textureCompressionBC requires all BC formats in Vulkan.
Missing BC formats added in this commit:
 - VK_FORMAT_BC1_RGB_UNORM_BLOCK
 - VK_FORMAT_BC1_RGB_SRGB_BLOCK

Fixes: fa6fa8c19e ("kk: BCn Formats")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38014>
2025-10-22 21:08:27 +00:00
Lionel Landwerlin
f3df267735 brw: handle GLSL/GLSL tessellation parameters
Apparently various tessellation parameters come specified from
TESS_EVAL stage in GLSL while they come from the TESS_CTRL stage in
HLSL.

We switch to store the tesselation params more like shader_info with 0
values for unspecified fields. That let's us merge it with a simple OR
with values from from tcs/tes and the resulting merge can be used for
state programming.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: a91e0e0d61 ("brw: add support for separate tessellation shader compilation")
Fixes: 50fd669294 ("anv: prep work for separate tessellation shaders")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37979>
2025-10-22 20:48:59 +00:00
Lionel Landwerlin
8d05b7b72e anv: rename structure holding 3DSTATE_WM_DEPTH_STENCIL state
Cc stable for the next commit.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37979>
2025-10-22 20:48:59 +00:00
Mel Henning
fafb81cd02 treewide: Use vk_collect_dependency_info_src_stages
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Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37961>
2025-10-22 19:22:17 +00:00
Mel Henning
90d17c0088 vulkan: Add vk_collect_dependency_info_src_stages
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37961>
2025-10-22 19:22:17 +00:00
Valentine Burley
fd2fa0fbc9 tu: Fix maxVariableDescriptorCount with inline uniform blocks
It must not be larger than maxInlineUniformBlockSize.

Fixes VKCTS 1.4.4.0's
dEQP-VK.api.maintenance3_check.support_count_inline_uniform_block*.

Cc: mesa-stable

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38002>
2025-10-22 18:14:00 +00:00
Valentine Burley
17e25b4983 tu: Fix indexing with variable descriptor count
Based on RADV.
The Vulkan spec says:
    "If bindingCount is zero or if this structure is not included in
     the pNext chain, the VkDescriptorBindingFlags for each descriptor
     set layout binding is considered to be zero. Otherwise, the
     descriptor set layout binding at
     VkDescriptorSetLayoutCreateInfo::pBindings[i] uses the flags in
     pBindingFlags[i]."

Fixes dEQP-VK.api.maintenance3_check.* in VKCTS 1.4.4.0.

Cc: mesa-stable

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38002>
2025-10-22 18:14:00 +00:00
Simon Perretta
ff51e6dc9e nir: commonize barycentric intrinsic opt pass
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Introduces an opt pass that attempts to optimize
load_barycentric_at_{sample,offset} with simpler load_barycentric_*
equivalents where possible, and optionally lowers
load_barycentric_at_sample to load_barycentric_at_offset with a position
derived from the sample ID instead.

Signed-off-by: Simon Perretta <simon.perretta@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37658>
2025-10-22 16:48:01 +00:00
Caio Oliveira
e38491eb18 mesa/st: Lower to ALU scalar after fp64 subgroup lowering
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The subgroup lowering may generate new fp64 vector operations, so
ensure that those are lowered before calling nir_lower_doubles().

Issue spotted by Georg Lehmann.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38003>
2025-10-22 15:35:34 +00:00
Isaac Marovitz
fa6fa8c19e kk: BCn Formats
Signed-off-by: Isaac Marovitz <isaacryu@icloud.com>
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37967>
2025-10-22 15:21:29 +00:00
Jarrett Johnson
a62f285607 kk: advertise multiDrawIndirect
Reviewed-by: Aitor Camacho <aitor@lunarg.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37962>
2025-10-22 15:08:13 +00:00
Olivia Lee
bca29b1c92 hk: fix data race when initializing poly_heap
hk_heap is called during command buffer recording, which may be
concurrent, so writing dev->heap without synchronization is a data race.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: 5bc8284816 ("hk: add Vulkan driver for Apple GPUs")
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37973>
2025-10-22 14:54:24 +00:00
Benjamin Cheng
b6d6c1af73 radv/video_enc: Cleanup slice count assert
This was left over when first enabling multiple slice encoding.

Fixes: 63e952ff2c ("radv/video: Support encoding multiple slices")
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37999>
2025-10-22 14:31:45 +00:00
Alyssa Rosenzweig
05481f56a0 brw: use the right int8/int16 division lowering
lowering bitsize before lowering idiv is silly, since then it forces us
down the software int32 division path instead of the much faster
int8/int16 lowered path. Relevant CTS tests:

dEQP-VK.spirv_assembly.type.scalar.i16.div_comp,
dEQP-VK.spirv_assembly.type.scalar.i8.rem_comp,

Go from:

SIMD8 shader: 46 instructions. 1 loops. 4716 cycles. 0:0 spills:fills
SIMD8 shader: 1008 instructions. 0 loops. 3600 cycles. 0:0 spills:fills, 8 sends

to:

SIMD8 shader: 17 instructions. 1 loops. 2556 cycles. 0:0 spills:fills
SIMD8 shader: 464 instructions. 0 loops. 1394 cycles. 0:0 spills:fills, 8 sends

No stats change on fossil-db (which has very little int8/int16 and even
less integer division, apparently).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37966>
2025-10-22 10:00:36 -04:00
Aksel Hjerpbakk
c2a6fb6419 panvk: cull semaphores in unrelated subqueues
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Skip waiting/signaling on semaphores with stages not related
to a given subqueue

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37810>
2025-10-22 11:48:50 +00:00
Aksel Hjerpbakk
1381228329 panvk: refactor vk_stage_to_subqueue_mask
- rename vk_stage_to_subqueue_mask -> vk_stages_to_subqueue_mask
- handle stage masks instead of single stages.
- Add which sync scope it is reading to better reason with the mask semantics.
- Handle ALL_COMMANDS as well as TOP/BOTTOM (using sync scopes)
- add timestamp utility vk_stage_to_timestamp_subqueue_mask

Reviewed-by: Lars-Ivar Hesselberg Simonsen <lars-ivar.simonsen@arm.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37810>
2025-10-22 11:48:50 +00:00
Julian Orth
9fde755357 kopper: disable color management for wayland surfaces
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Otherwise clients cannot use color management themselves.

Signed-off-by: Julian Orth <ju.orth@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37693>
2025-10-22 10:22:41 +00:00
Pierre-Eric Pelloux-Prayer
90103fe618 radeonsi: propagate shader updates for merged shaders
In case of merged shaders (eg: VS+GS), a change to VS should trigger
a GS update.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13935
Fixes: b1a34ac95d ("radeonsi: change do_update_shaders boolean to a bitmask")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37882>
2025-10-22 09:45:49 +00:00
Pierre-Eric Pelloux-Prayer
091f18ea57 radeonsi: set VS dirty bit from si_vs_key_update_inputs
Since it has to be done for every caller we might as well
do it from a single place.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37882>
2025-10-22 09:45:49 +00:00
Pierre-Eric Pelloux-Prayer
d3f8571e84 radeonsi: limit the sqtt buffer size
We don't want the buffer size to wraparound to 0.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37882>
2025-10-22 09:45:49 +00:00
Lars-Ivar Hesselberg Simonsen
a7bf37e3bd panvk/v9+: Reduce maxBoundDescriptorSets to 7
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Until now, the driver has been using a single set for internal state
while leaving maxBoundDescriptorSets to the remaining 15.

This gives us no room for optimizations of driver sets, which might
become an issue in the future.

To remedy this, we therefore reduce maxBoundDescriptorSets to 7. This
aligns with the proprietary driver and gives us the space to optimize
the driver sets.

We might increase this in the future if we see that we don't need all
the driver sets we now reserve.

Reviewed-by: John Anthony <john.anthony@arm.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Olivia Lee <olivia.lee@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37978>
2025-10-22 10:38:35 +02:00
Eric Engestrom
4ab65cdaa4 docs: update/fix vk spec urls
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37993>
2025-10-22 09:23:34 +02:00
Faith Ekstrand
efbecd93ba util: Build util/cache_ops_x86.c with -msse2
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__builtin_ia32_clflush() requires -msse2 so we need to set -msse2 at
least for building that file.  Fortunately, there are no GPUs that
actually need userspace cache flushing that can ever be bolted onto a
pre-SSE2 x86 CPUs.

Fixes: 555881e574 ("util/cache_ops: Add some cache flush helpers")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14134
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37958>
2025-10-22 03:36:10 +00:00
Faith Ekstrand
3739d7a90c util: Don't advertise cache ops on x86 without SSE2
Fixes: 555881e574 ("util/cache_ops: Add some cache flush helpers")
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37958>
2025-10-22 03:36:10 +00:00
Olivia Lee
a410d90fd2 panfrost: fix cl_local_size for precompiled shaders
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nir_lower_compute_system_values will attempt to lower
load_workgroup_size unless workgroup_size_variable is set. For precomp
shaders, the workgroup size is set statically for each entrypoint by
nir_precompiled_build_variant. Because we call
lower_compute_system_values early, it sets the workgroup size to zero.
Temporarily setting workgroup_size_variable while we are still
processing all the entrypoints together inhibits this.

Signed-off-by: Olivia Lee <olivia.lee@collabora.com>
Fixes: 20970bcd96 ("panfrost: Add base of OpenCL C infrastructure")
Reviewed-by: Eric R. Smith <eric.smith@collabora.com>
Reviewed-by: Mary Guillemard <mary.guillemard@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37799>
2025-10-22 00:15:49 +00:00
Aitor Camacho
02a1ec1021 kk: Hash vertex input state
We embed vertex fetching into vertex shaders and therefore
we require hashing that state so the hash works as expected.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37992>
2025-10-21 23:59:33 +00:00
Lorenzo Rossi
dc0dcc993b nvk: implement VK_EXT_discard_rectangles
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Signed-off-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33476>
2025-10-21 23:17:38 +00:00
Lorenzo Rossi
4c62e09505 vulkan: increase MESA_VK_MAX_DISCARD_RECTANGLES
Turing and newer Nvidia cards can work with up to 8 discard rectangles

Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Signed-off-by: Lorenzo Rossi <git@rossilorenzo.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33476>
2025-10-21 23:17:38 +00:00
Rhys Perry
b18421ae3d amd/lower_mem_access_bit_sizes: fix shared access when bytes<bit_size/8
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This can happen with (for example) 32x2 loads with
align_mul=4,align_offset=2.

This patch does bit_size=min(bit_size,bytes) to prevent num_components
from being 0.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 52cd5f7e69 ("ac/nir_lower_mem_access_bit_sizes: Split unsupported shared memory instructions")
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37953>
2025-10-21 22:10:34 +00:00