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anv: prep work for separate tessellation shaders

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34872>
This commit is contained in:
Lionel Landwerlin 2025-05-08 12:16:06 +03:00 • committed by Marge Bot
parent a91e0e0d61
commit 50fd669294
4 changed files with 27 additions and 13 deletions
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1
src/intel/vulkan/anv_nir.h
View file

@ -115,6 +115,7 @@ bool anv_nir_apply_pipeline_layout(nir_shader *shader,
void *push_map_mem_ctx);
struct anv_nir_push_layout_info {
bool separate_tessellation;
bool fragment_dynamic;
bool mesh_dynamic;
};

20
src/intel/vulkan/anv_nir_compute_push_layout.c
View file

@ -133,8 +133,11 @@ anv_nir_compute_push_layout(nir_shader *nir,
}
const bool needs_dyn_tess_config =
nir->info.stage == MESA_SHADER_TESS_CTRL &&
container_of(prog_key, struct brw_tcs_prog_key, base)->input_vertices == 0;
(nir->info.stage == MESA_SHADER_TESS_CTRL &&
(container_of(prog_key, struct brw_tcs_prog_key, base)->input_vertices == 0 ||
push_info->separate_tessellation)) ||
(nir->info.stage == MESA_SHADER_TESS_EVAL &&
push_info->separate_tessellation);
if (needs_dyn_tess_config) {
const uint32_t tess_config_start = anv_drv_const_offset(gfx.tess_config);
const uint32_t tess_config_end = tess_config_start +
@ -356,14 +359,19 @@ anv_nir_compute_push_layout(nir_shader *nir,
assert(n_push_ranges <= 4);
if (nir->info.stage == MESA_SHADER_TESS_CTRL && needs_dyn_tess_config) {
struct brw_tcs_prog_data *tcs_prog_data =
container_of(prog_data, struct brw_tcs_prog_data, base.base);
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(prog_data);
const uint32_t tess_config_offset =
anv_drv_const_offset(gfx.tess_config);
const uint32_t tess_config_offset = anv_drv_const_offset(gfx.tess_config);
assert(tess_config_offset >= push_start);
tcs_prog_data->tess_config_param = (tess_config_offset - push_start) / 4;
}
if (nir->info.stage == MESA_SHADER_TESS_EVAL && push_info->separate_tessellation) {
struct brw_tes_prog_data *tes_prog_data = brw_tes_prog_data(prog_data);
const uint32_t tess_config_offset = anv_drv_const_offset(gfx.tess_config);
assert(tess_config_offset >= push_start);
tes_prog_data->tess_config_param = (tess_config_offset - push_start) / 4;
}
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
struct brw_wm_prog_data *wm_prog_data =
container_of(prog_data, struct brw_wm_prog_data, base);

1
src/intel/vulkan/anv_pipeline.c
View file

@ -2281,6 +2281,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_base_pipeline *pipeline,
if (!anv_pipeline_base_has_stage(pipeline, s))
continue;
stages[s].prog_data.base.stage = s;
stages[s].cache_key.stage = s;
memcpy(stages[s].cache_key.sha1, sha1, sizeof(sha1));
}

18
src/intel/vulkan/genX_gfx_state.c
View file

@ -2435,20 +2435,23 @@ cmd_buffer_flush_gfx_runtime_state(struct anv_gfx_dynamic_state *hw_state,
}
#endif
/* If the pipeline uses a dynamic value of patch_control_points and either
* the pipeline change or the dynamic value change, check the value and
* reemit if needed.
/* If the pipeline uses a dynamic value of patch_control_points or the
* tessellation domain is dynamic and either the pipeline change or the
* dynamic value change, check the value and reemit if needed.
*/
const struct brw_tcs_prog_data *tcs_prog_data = get_gfx_tcs_prog_data(gfx);
const struct brw_tes_prog_data *tes_prog_data = get_gfx_tes_prog_data(gfx);
const bool tcs_dynamic =
tcs_prog_data && tcs_prog_data->input_vertices == 0;
if (tcs_dynamic &&
((gfx->dirty & ANV_CMD_DIRTY_HS) ||
const bool tes_dynamic =
tes_prog_data && tes_prog_data->base.vue_map.layout != INTEL_VUE_LAYOUT_FIXED;
if ((tcs_dynamic || tes_dynamic) &&
((gfx->dirty & (ANV_CMD_DIRTY_HS | ANV_CMD_DIRTY_DS)) ||
BITSET_TEST(dyn->dirty, MESA_VK_DYNAMIC_TS_PATCH_CONTROL_POINTS))) {
SET(TESS_CONFIG, tess_config,
intel_tess_config(dyn->ts.patch_control_points,
tcs_prog_data->instances,
0,
tes_prog_data->domain,
tcs_prog_data->base.vue_map.num_per_patch_slots,
tcs_prog_data->base.vue_map.num_per_vertex_slots,
tcs_prog_data->base.vue_map.builtins_slot_offset));
@ -3474,7 +3477,8 @@ cmd_buffer_gfx_state_emission(struct anv_cmd_buffer *cmd_buffer)
if (IS_DIRTY(TESS_CONFIG)) {
push_consts->gfx.tess_config = hw_state->tess_config;
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT |
VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
gfx->base.push_constants_data_dirty = true;
}