Commit graph

174586 commits

Author SHA1 Message Date
Christian Gmeiner
5a95280748 etnaviv: nir: lower nir_texop_txs
Non of the GPU models know at this time have hardware support to
retrieve the dimensions of a level of a texture. Do almost the
same as the binary blob and store the needed values as uniforms.

Passes dEQP-GLES3.functional.shaders.texture_functions.texturesize.*

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
88f399b651 etnaviv: nir: support intrinsic used for txs lowering
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
fb48d3d1da nir: add enta specific intrinsic used for txs lowering
Non of the know etnaviv GPUs support this feature in hardware
and the binary blob provides sizes via uniforms too.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Christian Gmeiner
65ffa5b0b8 etnaviv: move nir texture lowerings into one pass
This is just a prep commit to keep all texture related
lowerings in one c file.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24217>
2023-07-21 08:52:03 +00:00
Marcin Ślusarz
06046a02f8 anv: merge cases leading to the same code
Added in: 688968e888 ("anv: add support for direct descriptor in allocation/writes")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>
2023-07-21 07:22:22 +00:00
Marcin Ślusarz
0eb2679cdb anv: drop unused function
Added in: 02cecffe2b ("anv: add a pass to partially lower resource_intel")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>
2023-07-21 07:22:22 +00:00
Marcin Ślusarz
3c83ac8002 intel/compiler: remove redundant code
has_lsc is checked few lines above, so this code doesn't matter.

Added in: a358b97c58 ("intel/fs: optimize uniform SSBO & shared loads")

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24260>
2023-07-21 07:22:22 +00:00
Hyunjun Ko
e3ecba3266 anv: use ycbcr_info for P010 format
Since !24096 landed, we can just use ycbcr_info to get information
of an image of the P010 format.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24265>
2023-07-21 06:15:30 +00:00
M Henning
340df42977 nouveau: Delete the nouveau_compiler tool
It's TGSI only.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:36 +00:00
M Henning
b5a638454d nouveau: Drop BuildUtil::Location
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:36 +00:00
M Henning
73239d4029 nouveau: Drop BuildUtil::DataArray
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
51dfde7b96 nouveau: Drop ConverterCommon::Subroutine
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
c631635f43 nouveau: Drop tgsi support from nv50_ir_prog_info
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
38a96f79af nouveau: Delete nv50_ir_from_tgsi.cpp
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
9178b049cc nv50: Keep nir directly in nv50_program
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
M Henning
d00d967399 nvc0: Keep nir directly in nvc0_program
instead of under pipe_shader_state.

This makes it obvious that we never produce tgsi shaders since
c3cbe610 "nouveau: Delete the NV50_PROG_USE_TGSI env var."

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24175>
2023-07-21 02:40:35 +00:00
Mike Blumenkrantz
88bf4b61af zink: emit SpvCapabilitySampleMaskPostDepthCoverage with SpvExecutionModePostDepthCoverage
can't have one without the other

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24183>
2023-07-21 01:28:56 +00:00
Mike Blumenkrantz
d744bb5bfc zink: be even dumber about buffer refs when replacing storage
these extra checks can cause issues when multiple contexts and transfer
ops are involved

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24141>
2023-07-21 01:01:04 +00:00
Karol Herbst
23795dc318 nvc0: fix num_gprs for Volta+
Overallocating by 2 gprs for ugprs is a wild guess by me. It does make
sense though as each subgroup shares 64 ugprs and that's 2 per thread.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24261>
2023-07-20 23:19:58 +00:00
Karol Herbst
fa8634388b llvmpipe: enable system SVM
The API bits are already implemented in clover and rusticl and by
definition a CPU driver implements SVM.

This should allow anybody to work on proper SyCL/CHIP-SPV support for
rusticl running llvmpipe.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>
2023-07-20 23:00:24 +00:00
Karol Herbst
44e652af9a rusticl/mesa: make svm_migrate optional
It's just a hint and drivers might want to ignore implementing it for now.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24092>
2023-07-20 23:00:24 +00:00
Nanley Chery
99ffa4043e intel/isl: Add a score for DG2_RC_CCS
This enables the DG2 render compression modifier in anv. When I tested
this against vkcube, I observed that the full resolve which happened at
the end of every frame was converted to a partial resolve, allowing the
framebuffer to retain compression.

According to Caleb Callaway's testing, enabling this modifier positively
impacts the FPS of the following game benchmarks:

 - Strange Brigade.vk-g6              +12.78%
 - Strange Brigade.dx12vk-g6          + 9.33%
 - Shadow of the Tomb Raider.vk-g6-lx + 2.37%
 - Dota 2 (replay Jul 2020).vk-g6     + 2.28%

Thanks to Felix Degrood for pointing out that Strange Brigade would
benefit from this optimization.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:27 +00:00
Nanley Chery
15dec30877 intel/isl: Move the Tile4 modifier score case down
Group modifiers by platform first, then the score. I find it easier to
read this way.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:27 +00:00
Nanley Chery
d9bdffa708 intel: Describe modifier compression with booleans
Replace the aux_usage field with two booleans: one for render
compression and one for media compression.

This more accurately describes how CCS_E is used on gfx12. On those
platforms, the FCV feature may be enabled or disabled, but ISL's
modifier table has been using the FCV aux-usage for every gfx12 render
compression modifier. Instead, set the newly-added render compression
boolean to true.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:27 +00:00
Nanley Chery
37068e8aaf iris: Swap stencil and modifier aux assignment order
Makes the next patch clearer.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
f5f61c5bb7 hasvk: Delete modifier with aux code
Modifiers with compression are not supported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
2d7fc325d6 crocus: Delete modifier with aux code
Modifiers with compression are not supported.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
5568970d63 iris: Reduce accesses of mod_info->aux_usage
This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
569f80f2df anv: Reduce accesses of isl_mod_info->aux_usage
This field will be replaced in an upcoming patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
f2dab434d8 anv: Handle explicit surface layout of DG2_RC_CCS
We're going to enable the DG2 modifier. Account for the reduced plane
count that exists with it.

Also add an assert to make it clearer that the aux in use is CCS.
Otherwise, it may not be obvious because of the generic compression
names being used here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
47565d31e1 intel: Add and use isl_drm_modifier_get_plane_count
We're going to enable the DG2_RC_CCS modifier in anv. Add and use this
function to prepare for the new plane count that comes with that
modifier.

iris is left alone for now because it supports more modifiers than
isl_drm_modifier_get_score is aware of.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
e50af52e3d anv: Don't support ASTC images with modifiers
Before this change, anv_get_image_format_features2 reported support for
ASTC formats with any modifier (even those not supported by anv). But,
we didn't intend to support that compressed image format with modifiers.

With this change, the format feature function reports no support for
modifiers on ASTC-formatted images.

This prevents the next patch from causing assertion failures due to
unsupported modifiers.

Fixes: 355f318843 ("anv: Allow transfer-only linear ASTC images")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Nanley Chery
c042eb653d iris: Remap DRM_FORMAT_MOD_INVALID more often during import
We'd eventually like to use an ISL helper that doesn't support
DRM_FORMAT_MOD_INVALID. Prepare for this by replacing the invalid value
with the modifier associated with the BO's tiling in more cases.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24120>
2023-07-20 20:53:26 +00:00
Rohan Garg
ba071ee81c anv: use the correct GFX_VERx10 macro for WA
Fixes: 60b0d2c2cb ("add required invalidate/flush for Wa_14014427904")
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23937>
2023-07-20 20:25:12 +00:00
Rohan Garg
097f3b4a98 anv: use the WA infrastructure where possible when generating state
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23937>
2023-07-20 20:25:12 +00:00
Marek Olšák
54f18b5000 radeonsi: fix a CDNA regression breaking compute
reported internally

Fixes: 315231b5a5 - radeonsi: eliminate redundant compute SH register changes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24169>
2023-07-20 18:42:56 +00:00
Christian Gmeiner
019e5cbd39 nir/print: print instr pass_flags
From time to time it can be helpful to "see" the pass_flags.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24234>
2023-07-20 18:03:47 +00:00
Yiwei Zhang
a89752d630 turnip: flush cache for dstBuffer in vkCmdCopyQueryPoolResults
There can be other writes to the dstBuffer gated by proper barriers
beforehand.

TEST=dEQP-VK.pipeline.*.timestamp.* with Venus on Turnip

Fixes: 487aa807bd ("tu: Rewrite flushing to use barriers")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24245>
2023-07-20 16:28:17 +00:00
Alyssa Rosenzweig
950a0b6a63 ir2: Switch to nir_legacy
Addresses a2xx portion of #9051.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24118>
2023-07-20 15:50:54 +00:00
Alyssa Rosenzweig
ad214fcaf7 asahi: Advertise Z16_UNORM
This works (on the downstream kernel, anyway).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
0197d46b34 asahi: Execute preambles for background programs
This will be useful when spilling render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
9fbe2fdea0 asahi: Offset clear colour uniform by 4
Frees up u0_u1 for a bindless base address which will make render target
spilling easier to implement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
0597c100cc asahi: Ignore spilled render targets for background load
Nothing to reload.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
ef5a5e170f asahi: Permit meta shaders to use preambles
Preambles are occassionally useful with background programs.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:29 +00:00
Alyssa Rosenzweig
5f167c9f72 asahi: Lower multisample image stores
These will be used for spilling multisampled render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
ff16397912 asahi: Lower tilebuffer access for spilled RTs
Conceptually similar, we just don't have the tilebuffer available this time.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
66e8afe7c9 asahi: Extract some tilebuffer lowering code
In prep for spilling. No functional change.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
46b5406483 asahi: Ignore spilled render targets with partial renders
Partial renders exist to the spill the tilebuffer to memory, there's nothing to
do if it's already spilled (and would just waste memory bandwidth and create a
feedback loop).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
dc38f24de3 asahi: Ignore spilled render targets in EOT shaders
Regardless whether we implement Apple-style eMRT or something simpler, the EOT
shader isn't involved here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00
Alyssa Rosenzweig
73fb1543fd asahi: Do not support masking with spilled RTs
Extra complexity for this interaction, not worth it until we have an actual use
case IMHO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
2023-07-20 15:33:28 +00:00