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asahi: Offset clear colour uniform by 4

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Frees up u0_u1 for a bindless base address which will make render target
spilling easier to implement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>
This commit is contained in:
Alyssa Rosenzweig 2023-06-15 07:03:32 -04:00 • committed by Marge Bot
parent 0597c100cc
commit 9fbe2fdea0
2 changed files with 2 additions and 2 deletions
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2
src/asahi/lib/agx_meta.c
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@ -64,7 +64,7 @@ build_background_op(nir_builder *b, enum agx_meta_op op, unsigned rt,
} else {
assert(op == AGX_META_OP_CLEAR);
return nir_load_preamble(b, nr, 32, rt * 8);
return nir_load_preamble(b, nr, 32, 4 + (rt * 8));
}
}

2
src/gallium/drivers/asahi/agx_state.c
View file

@ -2380,7 +2380,7 @@ agx_build_meta(struct agx_batch *batch, bool store, bool partial_render)
needs_sampler = true;
} else if (key.op[rt] == AGX_META_OP_CLEAR) {
assert(batch->uploaded_clear_color[rt] && "set when cleared");
agx_usc_uniform(&b, 8 * rt, 8, batch->uploaded_clear_color[rt]);
agx_usc_uniform(&b, 4 + (8 * rt), 8, batch->uploaded_clear_color[rt]);
} else if (key.op[rt] == AGX_META_OP_STORE) {
struct pipe_image_view view =
image_view_for_surface(batch->key.cbufs[rt]);