Commit graph

75872 commits

Author SHA1 Message Date
Jason Ekstrand
569f70be56 vk/0.210.0: Rework copy/clear/blit API 2015-12-03 13:43:47 -08:00
Jason Ekstrand
4ab9391fbb vk/0.210.0: Rework dynamic states 2015-11-30 14:19:41 -08:00
Jason Ekstrand
73ef7d47d2 vk/0.210.0: Rework color blending enums 2015-11-30 13:49:28 -08:00
Jason Ekstrand
2c77b0cd01 gen7/8/cmd_buffer: Inline vk_to_gen_swizzle
It's currently unused on IVB so we get compiler warnings.
2015-11-30 13:29:51 -08:00
Jason Ekstrand
9b1cb8fdbc vk/0.210.0: Rework a few raster/input enums 2015-11-30 13:28:17 -08:00
Jason Ekstrand
a53f23d93f vk/0.210.0: Rework texture view component mapping 2015-11-30 13:06:12 -08:00
Jason Ekstrand
f1a7c7841f vk/0.210.0: Switch to the new VKAPI function decorations
While we're at it, we do a bunch of the VkResult -> void updates
2015-11-30 12:46:30 -08:00
Jason Ekstrand
a89a485e79 vk/0.210.0: Rename CmdBuffer to CommandBuffer 2015-11-30 11:48:08 -08:00
Jason Ekstrand
6a8a542610 vk/0.210.0: A pile of minor enum updates 2015-11-30 11:12:44 -08:00
Jason Ekstrand
3db43e8f3e vk/0.210.0: Switch to the new-style handle declarations 2015-11-30 10:58:02 -08:00
Jason Ekstrand
5cb57806b2 vk: Add connonical 0.170.2 and 0.210.0 headers
This is in preparation for the API update
2015-11-30 10:24:35 -08:00
Kristian Høgsberg Kristensen
d6d82f1ab3 vk: Fix 3DSTATE_WM_DEPTH_STENCIL for gen8
This packet is a different size on gen8 and we hit an assertion when we
try to merge a gen9 size dword array from the pipeline with the gen8
sized array we create from dynamic state.

Use a static assert in the merge macro and fix this issue by using different
wm_depth_stencil arrays on gen8 and gen9.
2015-11-26 10:11:52 -08:00
Kristian Høgsberg Kristensen
cd4721c062 vk: Add SKL support
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-11-25 22:34:10 -08:00
Kristian Høgsberg Kristensen
c445fa2f77 vk: Make entrypoint generator output gen9 entry points
Signed-off-by: Kristian Høgsberg Kristensen <kristian.h.kristensen@intel.com>
2015-11-25 20:58:25 -08:00
Kristian Høgsberg Kristensen
0e02a88ad4 vk: Add GEN9 pack header 2015-11-25 20:56:41 -08:00
Kristian Høgsberg Kristensen
0c59cb42b5 vk: Move all gen8 files to gen8 lib 2015-11-25 14:13:53 -08:00
Jason Ekstrand
179fc4aae8 Merge remote-tracking branch 'mesa-public/master' into vulkan
This pulls in nir cloning and some much-needed upstream refactors.
2015-11-23 14:03:47 -08:00
Jason Ekstrand
d9b8fde963 i965: Use NIR for lowering texture swizzle
Now that nir_lower_tex can do texture swizzle lowering, we can use that
instead of repeating more-or-less the same code in both backends.  This
both allows us to share code and means that things like the tg4
work-arounds are somewhat simpler because they don't have to take the
swizzle into account.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:07:32 -08:00
Jason Ekstrand
8537b4ab76 nir/lower_tex: Add support for lowering texture swizzle
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand
6921b17107 nir: Add a tex_instr_is_query helper
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand
7e83fd85aa nir: Add a ssa_def_rewrite_uses_after helper
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand
384396a69b nir: Use instr/if_rewrite in nir_ssa_def_rewrite_uses
nir_ssa_def_rewrite_uses is one of the older helpers in NIR and predated
both of those.  Now it can be substantially simplified.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand
03c9ad900e nir/validate: Validated dests after sources
Previously, if someone accidentally made an instruction that refers to its
own SSA destination, the validator wouldn't catch it.  The reason for this
is that it validated the destination too early and, by the time it got to
the source, the destination SSA value was already added to the set of seen
SSA values so it would assume that it came from some previous instruction.
By moving destination validation to be after source validation, the SSA
value is not in the list of seen values and the validator will catch
self-referential instructions.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
2015-11-23 11:04:49 -08:00
Jason Ekstrand
6c8ba59cff i965: Use nir_lower_tex for texture coordinate lowering
Previously, we had a rescale_texcoords helper in the FS backend for
handling rescaling of texture coordinates.  Now that we can do variants in
NIR, we can use nir_lower_tex to do the rescaling for us.  This allows us
to delete the i965-specific code and gives us proper TEXTURE_RECTANGLE and
GL_CLAMP handling in vertex and geometry shaders.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-23 11:04:49 -08:00
Jason Ekstrand
d065a93a3f i965/fs: Stomp the texture return type to UINT32 for resinfo messages
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-11-23 11:02:15 -08:00
Jason Ekstrand
042fa75e48 nir/lower_tex: Set the dest_type for txs instructions
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand
1417f6a216 nir/lower_tex: Report progress
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand
ce767bbdff i965: Move postprocess_nir to codegen time
This allows us to insert NIR passes between initial NIR compilation and
optimization (link time) and actual backend code-gen.  In particular, it
will allow us to do shader variants in NIR and share some of that shader
variant code between backends.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand
9cf108193b i965/nir: Split shader optimization and lowering into three stages
At the moment, brw_create_nir just calls the three stages in sequence so
there's not much difference.  Soon, however, we will want to start doing
variants in NIR at which point the postprocessing step will have to move
from shader create time to codegen time.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2015-11-23 11:02:15 -08:00
Jason Ekstrand
9d703de85a i965: Use ull immediates in brw_inst_bits
This fixes a regression introduced in b1a83b5d1 that caused basically all
shaders to fail to compile on 32-bit platforms.

Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2015-11-23 10:55:38 -08:00
Ilia Mirkin
e4c1221d36 docs: add missed freedreno features to relnotes
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
2015-11-23 12:32:54 -05:00
Ilia Mirkin
33dc9aac07 docs: update relnotes with new freedreno/a4xx support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 12:32:54 -05:00
Jose Fonseca
c9651f0264 svga: Add ASTC formats to format table.
Fixes build.  Otherwise untested.

Trivial.
2015-11-23 16:45:28 +00:00
Ilia Mirkin
754b26e76d freedreno/ir3: add support for a few gs5 ops
Tested on a4xx. This is part of the builtins added by ARB_gpu_shader5
and GLSL ES 3.10.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:16 -05:00
Ilia Mirkin
cca8dd4e93 ttn: fix UMSB conversion
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:16 -05:00
Ilia Mirkin
190acb34ca freedreno/a4xx: add ARB_texture_query_lod support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
f0e670bdd7 ttn: add LODQ support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
9761d5146f freedreno/a4xx: re-emit program on dirty framebuffer
The program emit depends on certain fb details. Make sure those get
updated when the fb changes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
81b16350fa freedreno/a4xx: use a factor of 32767 for snorm8 blending
It appears that the hardware wants the integer to be scaled the same way
that the hardware representation is. snorm16 uses one of the float
factors, so this is only relevant for snorm8.

This fixes a number of subcases of
  bin/fbo-blending-formats GL_EXT_texture_snorm

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2015-11-23 11:17:15 -05:00
Ilia Mirkin
6f17f19b17 freedreno/a4xx: only compute texture offset once for the view
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
f10bb0ac9e freedreno/a4xx: add ARB_texture_view support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
1b9992b803 freedreno/a4xx: add formats for ARB_texture_buffer_object_rgb32 support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
f9549d0a0f freedreno/a4xx: add ARB_texture_rgb10_a2ui support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
93905a8df1 freedreno/a4xx: add astc formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
6b21d3c92e st/mesa: add astc support
This doesn't account for the ldr/hdr distinction... that will probably
have to be exposed via a separate cap. When relevant hardware appears,
this can be worked out.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
3333977556 gallium: add ASTC formats
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-11-23 11:17:15 -05:00
Ilia Mirkin
1c7d0a6aa4 gallium/util: remove the fake format helpers for bptc and etc2
This was a silly hack that kept growing and growing. Instead, just write
NULLs for those functions. No need to have helpers that just assert(0)
when you call them.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-11-23 11:17:14 -05:00
Ilia Mirkin
c65bc2e805 freedreno/a4xx: support 16384 texels in buffer texture
Looks like the width field's bitmask was off-by-one.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:14 -05:00
Ilia Mirkin
99f12a3f1a freedreno/a4xx: add ARB_texture_buffer_range support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:14 -05:00
Ilia Mirkin
d4c40f99ab freedreno/a4xx: add polygon mode support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2015-11-23 11:17:14 -05:00