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i965: Move postprocess_nir to codegen time

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This allows us to insert NIR passes between initial NIR compilation and
optimization (link time) and actual backend code-gen.  In particular, it
will allow us to do shader variants in NIR and share some of that shader
variant code between backends.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
This commit is contained in:
Jason Ekstrand 2015-11-11 10:04:43 -08:00
parent 9cf108193b
commit ce767bbdff
4 changed files with 20 additions and 5 deletions
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11
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -43,6 +43,7 @@
#include "brw_wm.h"
#include "brw_fs.h"
#include "brw_cs.h"
#include "brw_nir.h"
#include "brw_vec4_gs_visitor.h"
#include "brw_cfg.h"
#include "brw_dead_control_flow.h"
@ -5430,13 +5431,16 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_wm_prog_key *key,
struct brw_wm_prog_data *prog_data,
const nir_shader *shader,
const nir_shader *src_shader,
struct gl_program *prog,
int shader_time_index8, int shader_time_index16,
bool use_rep_send,
unsigned *final_assembly_size,
char **error_str)
{
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_postprocess_nir(shader, compiler->devinfo, true);
/* key->alpha_test_func means simulating alpha testing via discards,
* so the shader definitely kills pixels.
*/
@ -5589,11 +5593,14 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_cs_prog_key *key,
struct brw_cs_prog_data *prog_data,
const nir_shader *shader,
const nir_shader *src_shader,
int shader_time_index,
unsigned *final_assembly_size,
char **error_str)
{
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_postprocess_nir(shader, compiler->devinfo, true);
prog_data->local_size[0] = shader->info.cs.local_size[0];
prog_data->local_size[1] = shader->info.cs.local_size[1];
prog_data->local_size[2] = shader->info.cs.local_size[2];

1
src/mesa/drivers/dri/i965/brw_nir.c
View file

@ -412,7 +412,6 @@ brw_create_nir(struct brw_context *brw,
nir = brw_preprocess_nir(nir, is_scalar);
nir = brw_lower_nir(nir, devinfo, shader_prog, is_scalar);
nir = brw_postprocess_nir(nir, devinfo, is_scalar);
return nir;
}

6
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -1931,13 +1931,17 @@ brw_compile_vs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_vs_prog_key *key,
struct brw_vs_prog_data *prog_data,
const nir_shader *shader,
const nir_shader *src_shader,
gl_clip_plane *clip_planes,
bool use_legacy_snorm_formula,
int shader_time_index,
unsigned *final_assembly_size,
char **error_str)
{
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_postprocess_nir(shader, compiler->devinfo,
compiler->scalar_stage[MESA_SHADER_VERTEX]);
const unsigned *assembly = NULL;
unsigned nr_attributes = _mesa_bitcount_64(prog_data->inputs_read);

7
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
View file

@ -30,6 +30,7 @@
#include "brw_vec4_gs_visitor.h"
#include "gen6_gs_visitor.h"
#include "brw_fs.h"
#include "brw_nir.h"
namespace brw {
@ -606,7 +607,7 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const struct brw_gs_prog_key *key,
struct brw_gs_prog_data *prog_data,
const nir_shader *shader,
const nir_shader *src_shader,
struct gl_shader_program *shader_prog,
int shader_time_index,
unsigned *final_assembly_size,
@ -616,6 +617,10 @@ brw_compile_gs(const struct brw_compiler *compiler, void *log_data,
memset(&c, 0, sizeof(c));
c.key = *key;
nir_shader *shader = nir_shader_clone(mem_ctx, src_shader);
shader = brw_postprocess_nir(shader, compiler->devinfo,
compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
prog_data->include_primitive_id =
(shader->info.inputs_read & VARYING_BIT_PRIMITIVE_ID) != 0;