Commit graph

220163 commits

Author SHA1 Message Date
Marek Olšák
52d5dfc7d3 Remove redundant BLAKE3_KEY_LEN32
it's the same number as BLAKE3_OUT_LEN32

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
699f9d7066 Inline _mesa_sha1_init/update/final functions
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
3ae8f910ad Inline SHA1* functions, remove sha1.h
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
a965ada6ee Inline mesa_sha1, SHA1_CTX
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
0da88d237a Inline SHA1_DIGEST_STRING_LENGTH
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
110632f702 Inline SHA1_DIGEST_LENGTH
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40383>
2026-03-23 07:03:27 +00:00
Marek Olšák
2283244975 nir: change export_amd intrinsics to use target instead of base
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40415>
2026-03-23 06:10:49 +00:00
Marek Olšák
b75a3112fd nir: change export_amd intrinsics to use enabled_channels instead of write_mask
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40415>
2026-03-23 06:10:49 +00:00
Zan Dobersek
e7f6c8ab7e fd: make RD dump output path configurable through FD_RD_DUMP_PATH
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Allow adjusting the location of RD dumps and trigger file through the
FD_RD_DUMP_PATH environment variable. When not present, the existing
defaults will be used.

Signed-off-by: Zan Dobersek <zdobersek@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40532>
2026-03-22 11:03:04 +00:00
Eric Engestrom
8c4e6aa4c0 docs: delete now-unused html_redirects extension
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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40559>
2026-03-22 10:25:39 +01:00
Eric Engestrom
2b5889697d docs: replace html redirects with http redirects
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40559>
2026-03-22 10:25:29 +01:00
Eric Engestrom
d81a70b3af docs: fix various pep8 issues
Missing second empty lines between top-level classes/functions,
spurious/unnecessary newlines, unused imports... just bunch of trivial
and non-controversial stuff.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40558>
2026-03-22 09:48:57 +01:00
Marek Olšák
f9a10c46fa nir/inline_uniforms: track visited state per component
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This prevents an instruction from being marked inlinable or non-inlinable
when only a subset of components meet that condition.

This might only be relevant for non-scalar ALU.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40413>
2026-03-21 17:55:40 +00:00
Marek Olšák
d9a2fac925 nir/inline_uniforms: update comments
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40413>
2026-03-21 17:55:40 +00:00
Marek Olšák
3b004ec60b nir/inline_uniforms: rename new_num -> new_num_uniforms
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40413>
2026-03-21 17:55:39 +00:00
Marek Olšák
727d663f79 nir/inline_uniforms: rename num_offsets -> num_uniforms
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40413>
2026-03-21 17:55:39 +00:00
pal1000
718afd787c clc: Fix static link with clang>=22
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Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15090

Backport-to: 26.0

Reviewed-by: Karol Herbst <kherbst@redhat.com>

Tested-by: Rudi Heitbaum <rudi@heitbaum.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40549>
2026-03-21 12:36:22 +00:00
Timothy Arceri
06fc27b5a4 nir: test loop analyze sets exact trip flags correctly
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Introduces new test helper to create loop with multiple terminators
and tests some scenaros to make sure exact trip flags are set
correctly.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32473>
2026-03-21 11:46:14 +00:00
Timothy Arceri
82b474c3fb nir: remove is_only_uniform_src() restriction
Loop analysis seems to have assumed we needed a const here to be
a useful loop, however this isn't true so drop the restriction.

This allows the optimisation from 6ca81adffc to become more powerful.

Shader-db results radeonsi:

TOTALS FROM AFFECTED SHADERS (19/168079)
  SGPRS: 904.00 -> 848.00 (-6.19 %)
  VGPRS: 712.00 -> 684.00 (-3.93 %)
  Spilled SGPRs: 0.00 -> 0.00 (0.00 %)
  Spilled VGPRs: 0.00 -> 0.00 (0.00 %)
  Private memory VGPRs: 0.00 -> 0.00 (0.00 %)
  Scratch size: 0.00 -> 0.00 (0.00 %) dwords per thread
  Code Size: 80340.00 -> 92980.00 (15.73 %) bytes
  Max Waves: 236.00 -> 238.00 (0.85 %)
  Outputs: 0.00 -> 0.00 (0.00 %)
  Patch Outputs: 0.00 -> 0.00 (0.00 %)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32473>
2026-03-21 11:46:14 +00:00
Rob Herring (Arm)
6b26cc2df3 ethosu: Fix buffer overrun in stridedslice
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The slice.begin array length matches the tensor depth which may be less
than 4.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
5e93ab5477 ethosu: Support ReLU activation for ADD ops
ReLU activations require the minimum to be set to the zero point.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
69d1da3518 teflon: Support ReLU activation for ADD ops
ADD operations can have fused ReLU activations. Add the setting to the
operation state.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
3780fb8494 ethosu: Handle IFM2 H/W/D broadcast
If the IFM and IFM2 dimensions are not the same, then the H/W/D broadcast
needs to be enabled.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:20 +00:00
Rob Herring (Arm)
1cb46e9304 ethosu: Handle reversing IFM and IFM2 operands
IFM2 must be scalar or smaller than IFM. If not, then the operands need
to be swapped.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
d962160e95 ethosu: Add scalar ADD support
An input tensor can contain a single scalar value to add to the IFM.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
5606fd1ea6 ethosu: Add support for 16-bit tensors
Ethos-U can support 16-bit tensors. So far the driver just assumed 8-bit
tensors.

There's a few cases where 32-bit tensors are supported, but exactly what
those are hasn't been determined, so just reject them for now.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:19 +00:00
Rob Herring (Arm)
7613788f06 teflon: Add support for setting the tensor type size
Drivers supporting different element sizes need to know the element type
size.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:18 +00:00
Rob Herring (Arm)
c29860e9e9 test_teflon: Add 32-bit integer output comparison
Add support for 32-bit integer output comparison. This fixes several
test failures for movenetlightning and movenetthunder.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:18 +00:00
Rob Herring (Arm)
ac9bb98991 test_teflon: Fix missing UInt16/Int16 output size
The output comparison expects number of elements, not bytes. Adjusting the
size was missed when adding UInt16/Int16 output comparisons.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:18 +00:00
Rob Herring (Arm)
6375db3fd3 test_teflon: Fix crash with read-only buffers
Some decomposed models have read-only input buffers which already have
data and don't need to be initialized.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40525>
2026-03-21 08:32:17 +00:00
Daniel Schürmann
4ca0eb9f54 nir: validate that loop continue statements always link to continue constructs
Some checks are pending
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Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
94f959972d nir: ensure that loop continue statements always link to continue constructs
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
0089d81fb3 nir/tests: change opt_loop_peel_initial_break test to not use nir_jump_continue
We are going to disallow continue statements without
loop continue constructs.

Replaced with a test that checks that the optimization is not
applied in absense of actual work after the conditional break.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
4b238690cb aco/tests: add and lower loop continue constructs in all tests which use continues
We are going to disallow continue statements without
loop continue constructs.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
53f2c405e1 lavapipe/rt: add and lower loop continue construct in traversal shaders
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
e99b57ae5b tu/rt: add and lower loop continue construct in traversal shaders
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
d909e14f30 ac: add and lower loop continue construct for streamout buffer info loop
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
ff8c8858dc nir/lower_goto_ifs: Add and lower loop continue constructs
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
b5a90522e0 dozen: add and lower loop continue construct
for dzn_nir_triangle_fan_prim_restart_rewrite_index_shader().

We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
7e6dfb9f74 dxil/nir: Remove nir_jump_continue from lower_subgroup_scan()
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
ebfb9b9479 tgsi_to_nir: Add and lower loop continue constructs
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
058d15fa11 radv/dgc: add and lower loop continue construct
We are going to disallow continue statements without
loop continue constructs.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
2d73dd15d6 radv/rt: add and lower loop continue construct in traversal shaders
We are going to disallow continue statements without
loop continue constructs.

Totals from 58 (0.07% of 84369) affected shaders: (Navi21)
Instrs: 2320937 -> 2318938 (-0.09%)
CodeSize: 12554896 -> 12546892 (-0.06%); split: -0.06%, +0.00%
SpillSGPRs: 116 -> 102 (-12.07%)
SpillVGPRs: 2648 -> 2627 (-0.79%)
Latency: 13440088 -> 13424694 (-0.11%)
InvThroughput: 3262579 -> 3259088 (-0.11%)
VClause: 69628 -> 69666 (+0.05%)
SClause: 51528 -> 51519 (-0.02%)
Copies: 203958 -> 203478 (-0.24%); split: -0.29%, +0.05%
Branches: 70777 -> 70400 (-0.53%)
PreSGPRs: 4768 -> 4660 (-2.27%)
VALU: 1537105 -> 1536899 (-0.01%); split: -0.02%, +0.01%
SALU: 340938 -> 339623 (-0.39%)
VMEM: 120339 -> 120286 (-0.04%)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Acked-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
f159669cf3 nir/lower_continue_constructs: Remove unnecessary handling of multiple continue statements
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Daniel Schürmann
31af989270 nir/lower_continue_constructs: Simplify loops before lowering continue constructs
The idea is inspired by LLVM's LoopSimplify pass. Before
lowering continue constructs, the pass now also lowers
all continue statements, leaving only the trivial continue.
This ensures that loops will always only have one back-edge.

Totals from 396 (0.47% of 84383) affected shaders: (Navi48)
Instrs: 900330 -> 899850 (-0.05%); split: -0.17%, +0.12%
CodeSize: 4727216 -> 4727508 (+0.01%); split: -0.13%, +0.13%
Latency: 7276816 -> 7097199 (-2.47%); split: -2.53%, +0.06%
InvThroughput: 1580718 -> 1558646 (-1.40%); split: -1.42%, +0.03%
VClause: 12872 -> 12879 (+0.05%); split: -0.01%, +0.06%
SClause: 22237 -> 22240 (+0.01%); split: -0.00%, +0.02%
Copies: 67359 -> 65723 (-2.43%); split: -2.56%, +0.14%
Branches: 24252 -> 24163 (-0.37%); split: -0.52%, +0.15%
PreSGPRs: 34371 -> 34399 (+0.08%)
PreVGPRs: 25268 -> 25280 (+0.05%); split: -0.00%, +0.05%
VALU: 512493 -> 511580 (-0.18%); split: -0.33%, +0.15%
SALU: 122767 -> 122993 (+0.18%); split: -0.13%, +0.32%
VMEM: 22181 -> 22213 (+0.14%)
SMEM: 41370 -> 41376 (+0.01%)

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39942>
2026-03-21 07:42:55 +00:00
Nanley Chery
558053ef20 isl: Apply VALIGN_8 fast-clear restriction on Xe3P+
Some checks are pending
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Bpec 57340 and HSD 22021327133 state that this restriction applies to
Xe3P+.

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15067
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40471>
2026-03-20 21:25:39 +00:00
Mary Guillemard
cba5841d61 nak: Do not allow load_helper_invocation reordering
Some checks are pending
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load_helper_invocation can not be reordered past a demote.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: 7ece220f96 ("nak/nir: Lower systm values before lowering I/O")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40543>
2026-03-20 20:19:35 +00:00
Mary Guillemard
c6d8f7ce0c nir/dead_cf: Add missing load_global_nv handling
This was missing when this intrinsic was added.
Fix some issue with FSI lowering and probably more.

Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: e779538ad2 ("nir: add nvidia IO intrinsics")
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40543>
2026-03-20 20:19:35 +00:00
Mary Guillemard
bb6fc8cc20 nir/dead_cf: Add missing load_global_bounded handling
Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: caa0854da8 ("nir: plumb load_global_bounded")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40543>
2026-03-20 20:19:34 +00:00
Mary Guillemard
6013667d61 nir/dead_cf: Add missing load_ssbo_ir3 handling
Signed-off-by: Mary Guillemard <mary@mary.zone>
Fixes: 0092edfec0 ("nir/dead_cf: Do not remove loops with loads that can't be reordered")
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Mel Henning <mhenning@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40543>
2026-03-20 20:19:34 +00:00