mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-03-22 20:20:37 +01:00
nak/nir: Lower systm values before lowering I/O
This way I/O lowering can lower the stuff we generate in lower_system_values(). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24998>
This commit is contained in:
Faith Ekstrand
Marge Bot
parent
abe9c1fea2
commit
7ece220f96
1 changed files with 114 additions and 114 deletions
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@ -316,6 +316,113 @@ nak_nir_isberd(nir_builder *b, nir_def *vertex)
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return nir_isberd_nv(b, idx);
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}
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static bool
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nak_nir_lower_system_value_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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b->cursor = nir_before_instr(instr);
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nir_def *val;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_layer_id: {
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const uint32_t addr = nak_varying_attr_addr(VARYING_SLOT_LAYER);
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val = nir_load_input(b, intrin->def.num_components, 32,
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nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_primitive_id: {
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assert(b->shader->info.stage == MESA_SHADER_TESS_CTRL ||
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b->shader->info.stage == MESA_SHADER_TESS_EVAL);
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nir_def *idx = nak_nir_isberd(b, nir_imm_int(b, 0));
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val = nir_load_per_vertex_input(b, 1, 32, idx, nir_imm_int(b, 0),
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.base = NAK_ATTR_PRIMITIVE_ID,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_front_face:
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case nir_intrinsic_load_instance_id:
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case nir_intrinsic_load_vertex_id: {
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const gl_system_value sysval =
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nir_system_value_from_intrinsic(intrin->intrinsic);
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const uint32_t addr = nak_sysval_attr_addr(sysval);
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val = nir_load_input(b, intrin->def.num_components, 32,
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nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_patch_vertices_in: {
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val = nir_load_sysval_nv(b, 32, .base = NAK_SV_VERTEX_COUNT,
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.access = ACCESS_CAN_REORDER);
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val = nir_extract_u8(b, val, nir_imm_int(b, 1));
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break;
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}
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case nir_intrinsic_load_subgroup_invocation:
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case nir_intrinsic_load_helper_invocation:
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case nir_intrinsic_load_invocation_id:
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case nir_intrinsic_load_local_invocation_index:
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case nir_intrinsic_load_local_invocation_id:
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case nir_intrinsic_load_workgroup_id:
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case nir_intrinsic_load_workgroup_id_zero_base:
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case nir_intrinsic_load_subgroup_eq_mask:
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case nir_intrinsic_load_subgroup_lt_mask:
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case nir_intrinsic_load_subgroup_le_mask:
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case nir_intrinsic_load_subgroup_gt_mask:
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case nir_intrinsic_load_subgroup_ge_mask: {
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const gl_system_value sysval =
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intrin->intrinsic == nir_intrinsic_load_workgroup_id_zero_base ?
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SYSTEM_VALUE_WORKGROUP_ID :
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nir_system_value_from_intrinsic(intrin->intrinsic);
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const uint32_t idx = nak_sysval_sysval_idx(sysval);
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nir_def *comps[3];
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assert(intrin->def.num_components <= 3);
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for (unsigned c = 0; c < intrin->def.num_components; c++) {
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comps[c] = nir_load_sysval_nv(b, 32, .base = idx + c,
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.access = ACCESS_CAN_REORDER);
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}
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val = nir_vec(b, comps, intrin->def.num_components);
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break;
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}
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case nir_intrinsic_is_helper_invocation: {
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/* Unlike load_helper_invocation, this one isn't re-orderable */
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val = nir_load_sysval_nv(b, 32, .base = NAK_SV_THREAD_KILL);
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break;
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}
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case nir_intrinsic_shader_clock:
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val = nir_load_sysval_nv(b, 64, .base = NAK_SV_CLOCK);
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val = nir_unpack_64_2x32(b, val);
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break;
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default:
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return false;
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}
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if (intrin->def.bit_size == 1)
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val = nir_i2b(b, val);
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nir_def_rewrite_uses(&intrin->def, val);
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return true;
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}
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static bool
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nak_nir_lower_system_values(nir_shader *nir)
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{
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return nir_shader_instructions_pass(nir, nak_nir_lower_system_value_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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}
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static bool
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lower_per_vertex_io_intrin(nir_builder *b,
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nir_intrinsic_instr *intrin,
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@ -582,113 +689,6 @@ nak_nir_lower_fs_outputs(nir_shader *nir)
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return true;
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}
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static bool
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nak_nir_lower_system_value_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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b->cursor = nir_before_instr(instr);
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nir_def *val;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_layer_id: {
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const uint32_t addr = nak_varying_attr_addr(VARYING_SLOT_LAYER);
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val = nir_load_input(b, intrin->def.num_components, 32,
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nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_primitive_id: {
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assert(b->shader->info.stage == MESA_SHADER_TESS_CTRL ||
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b->shader->info.stage == MESA_SHADER_TESS_EVAL);
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nir_def *idx = nak_nir_isberd(b, nir_imm_int(b, 0));
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val = nir_load_per_vertex_input(b, 1, 32, idx, nir_imm_int(b, 0),
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.base = NAK_ATTR_PRIMITIVE_ID,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_front_face:
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case nir_intrinsic_load_instance_id:
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case nir_intrinsic_load_vertex_id: {
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const gl_system_value sysval =
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nir_system_value_from_intrinsic(intrin->intrinsic);
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const uint32_t addr = nak_sysval_attr_addr(sysval);
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val = nir_load_input(b, intrin->def.num_components, 32,
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nir_imm_int(b, 0), .base = addr,
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.dest_type = nir_type_int32);
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break;
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}
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case nir_intrinsic_load_patch_vertices_in: {
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val = nir_load_sysval_nv(b, 32, .base = NAK_SV_VERTEX_COUNT,
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.access = ACCESS_CAN_REORDER);
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val = nir_extract_u8(b, val, nir_imm_int(b, 1));
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break;
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}
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case nir_intrinsic_load_subgroup_invocation:
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case nir_intrinsic_load_helper_invocation:
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case nir_intrinsic_load_invocation_id:
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case nir_intrinsic_load_local_invocation_index:
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case nir_intrinsic_load_local_invocation_id:
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case nir_intrinsic_load_workgroup_id:
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case nir_intrinsic_load_workgroup_id_zero_base:
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case nir_intrinsic_load_subgroup_eq_mask:
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case nir_intrinsic_load_subgroup_lt_mask:
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case nir_intrinsic_load_subgroup_le_mask:
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case nir_intrinsic_load_subgroup_gt_mask:
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case nir_intrinsic_load_subgroup_ge_mask: {
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const gl_system_value sysval =
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intrin->intrinsic == nir_intrinsic_load_workgroup_id_zero_base ?
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SYSTEM_VALUE_WORKGROUP_ID :
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nir_system_value_from_intrinsic(intrin->intrinsic);
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const uint32_t idx = nak_sysval_sysval_idx(sysval);
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nir_def *comps[3];
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assert(intrin->def.num_components <= 3);
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for (unsigned c = 0; c < intrin->def.num_components; c++) {
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comps[c] = nir_load_sysval_nv(b, 32, .base = idx + c,
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.access = ACCESS_CAN_REORDER);
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}
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val = nir_vec(b, comps, intrin->def.num_components);
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break;
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}
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case nir_intrinsic_is_helper_invocation: {
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/* Unlike load_helper_invocation, this one isn't re-orderable */
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val = nir_load_sysval_nv(b, 32, .base = NAK_SV_THREAD_KILL);
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break;
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}
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case nir_intrinsic_shader_clock:
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val = nir_load_sysval_nv(b, 64, .base = NAK_SV_CLOCK);
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val = nir_unpack_64_2x32(b, val);
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break;
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default:
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return false;
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}
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if (intrin->def.bit_size == 1)
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val = nir_i2b(b, val);
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nir_def_rewrite_uses(&intrin->def, val);
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return true;
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}
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static bool
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nak_nir_lower_system_values(nir_shader *nir)
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{
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return nir_shader_instructions_pass(nir, nak_nir_lower_system_value_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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NULL);
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}
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static nir_mem_access_size_align
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nak_mem_access_size_align(nir_intrinsic_op intrin,
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uint8_t bytes, uint8_t bit_size,
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@ -771,6 +771,13 @@ nak_postprocess_nir(nir_shader *nir,
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OPT(nir, nir_lower_indirect_derefs, 0, UINT32_MAX);
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if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
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OPT(nir, nir_lower_tess_coord_z,
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nir->info.tess._primitive_mode == TESS_PRIMITIVE_TRIANGLES);
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}
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OPT(nir, nak_nir_lower_system_values);
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switch (nir->info.stage) {
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case MESA_SHADER_VERTEX:
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OPT(nir, nak_nir_lower_vs_inputs);
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@ -796,13 +803,6 @@ nak_postprocess_nir(nir_shader *nir,
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unreachable("Unsupported shader stage");
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}
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if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
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OPT(nir, nir_lower_tess_coord_z,
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nir->info.tess._primitive_mode == TESS_PRIMITIVE_TRIANGLES);
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}
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OPT(nir, nak_nir_lower_system_values);
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nak_optimize_nir(nir, nak);
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do {
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