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isl: Apply VALIGN_8 fast-clear restriction on Xe3P+
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Bpec 57340 and HSD 22021327133 state that this restriction applies to
Xe3P+.

Ref: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15067
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40471>
This commit is contained in:
Nanley Chery 2026-03-17 11:54:33 -04:00 • committed by Marge Bot
parent cba5841d61
commit 558053ef20
1 changed files with 8 additions and 4 deletions
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12
src/intel/isl/isl_gfx20.c
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@ -240,14 +240,18 @@ isl_gfx20_choose_image_alignment_el(const struct isl_device *dev,
/* WA_22018390030:
*
* Don't choose VALIGN_4 on Xe2 for color, non-volumetric, Tile4 surfaces
* which can be fast cleared. We choose the next smallest option instead,
* VALIGN_8.
* Don't choose VALIGN_4 on Xe2 for color, non-volumetric, Tile4
* surfaces which can be fast cleared. We choose the next smallest
* option instead, VALIGN_8.
*
* Bspec 57340 and HSD 22021327133 state that this also applies to
* Xe3P+.
*/
if (!INTEL_DEBUG(DEBUG_NO_FAST_CLEAR) &&
intel_needs_workaround(dev->info, 22018390030) &&
tiling == ISL_TILING_4 &&
info->dim != ISL_SURF_DIM_3D) {
assert(intel_needs_workaround(dev->info, 22018390030) ||
ISL_GFX_VER(dev) >= 35);
image_align_el->h = 8;
}
} else if (fmtl->bpb >= 64) {