For some reason, I thought that function was shared with i915tex... The good
news is that i965 gets to keep the lower pitch alignment requirements.
Thanks to Todd Merrill for pointing out the problem on IRC.
mipmap pitches must account for the device alignment requirements, which
used to be fairly simple; just align to a 4-byte boundary. However, to allow
textures to be drawn to under TTM, they now need to be aligned to a 64-byte
boundary. Placing all of the alignment constraints in a single function
allows this new constraint to be applied uniformly.
There was some pitch constraining code in intel_miptree_create, but that was
modifying the pitch long after the miptree had been layed out, so it only
served to wreck the mipmap and cause rendering errors.
(cherry picked from commit a183efc132 with manual
changes for mesa_7_0_branch by Michel Dänzer. One side effect of this is that
i965 also aligns the pitch of 2D textures to multiples of 64 bytes, hopefully
that won't cause any issues)
- return GL_INVALID_OPERATION instead of GL_INVALID_VALUE if location is bad
- correct the type-checking of uniforms from my previous commit
- accept location of -1 in _mesa_uniform_matrix
- fix sizes for GL_FLOAT_MAT2x3 and GL_FLOAT_MAT4x3 in sizeof_glsl_type
- fix size returns in _mesa_get_active_attrib
- fix out-of-bounds array access to vec_types in _mesa_get_active_attrib
- fix queries of matrix uniforms in _mesa_get_uniformfv
- fix _mesa_get_uniformfv to only return one base, even from an array
- allow location == -1 in _mesa_uniform
- validate types in _mesa_uniform
- allow array overruns in _mesa_uniform
primitive needs to include the begin/end flags (broken since vbo-0.2). Should
fix missing first/last line segment on gamma, i810, i915, mga, r200, radeon,
s3v, savage, unichrome (r300 already correct). Tested on r200, fixes#13527.
