Commit graph

186606 commits

Author SHA1 Message Date
Mark Janes
4acea392af intel/compiler: drop unused ray-tracing fields from cache hash
The compiler only references `intel_device_info->subslice_masks` for
ray tracing workloads.  Platforms which lack raytracing support can
share a cache even if they differ on this field.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28311>
2024-03-22 00:01:28 +00:00
Kenneth Graunke
9a72116367 intel/brw: Unify DF and Q/UQ lowering for MOV
Using the new unsupported_64bit_type helper.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Kenneth Graunke
97c7d5113d intel/brw: Use correct execution pipe for lowering SEL on DF
This is a float operation, let's keep it on the float pipe.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Kenneth Graunke
26d65e96dd intel/brw: Assert that min/max are not happening in 64-bit SEL lowering
These aren't handled, only pure selects.

Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Kenneth Graunke
a2c2a7bc00 intel/brw: Fix check for 64-bit SEL lowering types
The 64-bit type lowering for SEL in opt_algebraic had a pre-existing bug
where it only triggered when 64-bit float _and_ integer types were
unsupported.  Meteorlake supports 64-bit float but not integer, so we
need to lower Q/UQ in that case still.

When I moved this to a later pass, opt_peephole_sel started generating
Q/UQ SEL instructions which were failing to be lowered.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/10867
Fixes: ea423aba1b ("intel/brw: Split out 64-bit lowering from algebraic optimizations")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28328>
2024-03-21 23:25:56 +00:00
Dylan Baker
75ede9d9bc intel/brw: track last successful pass and leave the loop early
This is similar to what RADV implements using the NIR_LOOP_PASS
helpers. I have not used those helpers for a couple of reasons:

 1. They use the pointer to the optimization function, which doesn't
    work if the same function is called multiple times in one invocation
    of the loop (fixable)
 2. After fixing them, due to Intel's use of sub-expressions, the amount
    of code added to wrap the shared macro becomes more than simply
    reimplementing them for the Intel compiler

On most workloads the results are a wash, but on compile heavy
workloads like Cyberpunk 2077 and Rise of the Tomb Raider, I saw
fossil-db runtimes fall by 1-2% on my ICL, with no changes to the
compiled shaders. Caio saw closer to 2.5% on TGL.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27510>
2024-03-21 23:02:32 +00:00
Caio Oliveira
b2ee98d2db intel/brw: Handle Xe2 in brw_fs_opt_zero_samples
The mlen tracking is in REG_SIZE units, but in Xe2 each GRF has
doubled the size.  The optimization can only elide full GRFs, so
round down the amount of trailing zeros to ensure the optimization
will remove only full GRFs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28279>
2024-03-21 22:38:54 +00:00
Ian Romanick
cd70e49394 intel/brw: Allow SIMD16 F and HF type conversion moves
On DG2, the lowering generated for these MOV instructions is
**awful**. The original SIMD16 MOV

    { 18}   67: mov(16) vgrf54+0.0:HF, vgrf46+0.0:F NoMask group0

is lowered to SIMD8 MOVs:

    { 18}  118: mov(8) vgrf54+0.0:HF, vgrf46+0.0:F NoMask group0
    { 18}  119: mov(8) vgrf54+0.16:HF, vgrf46+1.0:F NoMask group8

These MOVs violate Gfx12.5 region restrictions, so these are further
lowered:

    { 17}  119: mov(8) vgrf83<2>:HF, vgrf46+0.0:F NoMask group0
    { 19}  120: mov(8) vgrf54+0.0:UW, vgrf83<2>:UW NoMask group0
    { 19}  122: mov(8) vgrf84<2>:HF, vgrf46+1.0:F NoMask group8
    { 19}  123: mov(8) vgrf54+0.16:UW, vgrf84<2>:UW NoMask group8

The shader-db and fossil-db results are nothing to get excited
about. However, the affect on vk_cooperative_matrix_perf is substantial. In one subtest

shader: shaders/shmemfp16.spv

cooperativeMatrixProps = 8x8x16   A = float16_t B = float16_t C = float16_t D = float16_t scope = subgroup
TILE_M=128 TILE_N=128, TILE_K=32 BLayout=0

performance on my DG2 improved by ~60% due to a MASSIVE reduction in spills and fills:

-Native code for unnamed compute shader (null) (src_hash 0x00000000) (sha1 c6a41b1c4e7aa2da327a39a70ed36c822a4b172f)
-SIMD32 shader: 32484 instructions. 1 loops. 1893868 cycles. 737:1820 spills:fills, 442 sends, scheduled with mode none. Promoted 1 constants. Compacted 519744 to 492224 bytes (5%)
-   START B0 (20782 cycles)
+Native code for unnamed compute shader (null) (src_hash 0x00000000) (sha1 621e960daad5b5579b176717f24a315e7ea560a1)
+SIMD32 shader: 23918 instructions. 1 loops. 1089894 cycles. 432:1166 spills:fills, 442 sends, scheduled with mode none. Promoted 1 constants. Compacted 382688 to 353232 bytes (8%)

shader-db:

All Gfx9 and later platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19656270 -> 19653981 (-0.01%)
instructions in affected programs: 61810 -> 59521 (-3.70%)
helped: 116 / HURT: 0

total cycles in shared programs: 823368888 -> 823375854 (<.01%)
cycles in affected programs: 1165284 -> 1172250 (0.60%)
helped: 51 / HURT: 57

fossil-db:

DG2 and Meteor Lake had similar results. (Meteor Lake shown)
*** Shaders only in 'before' results are ignored:
fossil-db/steam-dxvk/total_war_warhammer3/2a3ed2ca632a7cb7/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/18b9d4a3b1961616/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/04ac9f3146a6db19/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/f37ebec6aa1b379a/fs.32,
fossil-db/steam-dxvk/total_war_warhammer3/255c987feb0d4310/fs.32, and 25
more
from 1 apps: fossil-db/steam-dxvk/total_war_warhammer3

Totals:
Instrs: 160946537 -> 160928389 (-0.01%); split: -0.01%, +0.00%
Cycles: 14125908620 -> 14125873958 (-0.00%); split: -0.00%, +0.00%

Totals from 1002 (0.15% of 652134) affected shaders:
Instrs: 411261 -> 393113 (-4.41%); split: -4.41%, +0.00%
Cycles: 16676735 -> 16642073 (-0.21%); split: -0.48%, +0.27%

Tiger Lake
Totals:
Instrs: 164511816 -> 164497202 (-0.01%); split: -0.01%, +0.00%
Cycles: 13801675722 -> 13801629397 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 7955168 -> 7955152 (-0.00%)
Send messages: 8544494 -> 8544486 (-0.00%)

Totals from 997 (0.15% of 651454) affected shaders:
Instrs: 460820 -> 446206 (-3.17%); split: -3.17%, +0.00%
Cycles: 16265514 -> 16219189 (-0.28%); split: -0.84%, +0.56%
Subgroup size: 17552 -> 17536 (-0.09%)
Send messages: 26045 -> 26037 (-0.03%)

Ice Lake
Totals:
Instrs: 165504747 -> 165489970 (-0.01%); split: -0.01%, +0.00%
Cycles: 15145244554 -> 15145149627 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 8107032 -> 8107016 (-0.00%)
Send messages: 8598680 -> 8598672 (-0.00%)
Spill count: 45427 -> 45423 (-0.01%)
Fill count: 74749 -> 74747 (-0.00%)

Totals from 1125 (0.17% of 656115) affected shaders:
Instrs: 521676 -> 506899 (-2.83%); split: -2.83%, +0.00%
Cycles: 19555434 -> 19460507 (-0.49%); split: -0.59%, +0.10%
Subgroup size: 21616 -> 21600 (-0.07%)
Send messages: 28623 -> 28615 (-0.03%)
Spill count: 603 -> 599 (-0.66%)
Fill count: 1362 -> 1360 (-0.15%)

Skylake
*** Shaders only in 'after' results are ignored:
fossil-db/steam-native/red_dead_redemption2/cef460b80bad8485/fs.16,
fossil-db/steam-native/red_dead_redemption2/cd5fe081e2e5529d/fs.16
from 1 apps: fossil-db/steam-native/red_dead_redemption2

Totals:
Instrs: 141607617 -> 141593776 (-0.01%); split: -0.01%, +0.00%
Cycles: 14257812441 -> 14257661671 (-0.00%); split: -0.00%, +0.00%
Subgroup size: 7743752 -> 7743736 (-0.00%)
Send messages: 7552728 -> 7552720 (-0.00%)
Spill count: 43660 -> 43661 (+0.00%)
Fill count: 71301 -> 71303 (+0.00%)

Totals from 1017 (0.16% of 636964) affected shaders:
Instrs: 392454 -> 378613 (-3.53%); split: -3.53%, +0.00%
Cycles: 16622974 -> 16472204 (-0.91%); split: -1.04%, +0.13%
Subgroup size: 19840 -> 19824 (-0.08%)
Send messages: 23021 -> 23013 (-0.03%)
Spill count: 484 -> 485 (+0.21%)
Fill count: 1155 -> 1157 (+0.17%)

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28281>
2024-03-21 15:12:58 -07:00
Ian Romanick
66dc6e07f5 intel/brw: Fix handling of accumulator register numbers
Folks, there's more than one accumulator. In general, when the
register file is ARF, the upper 4 bits of the register number specify
which ARF, and the lower 4 bits specify which one of that ARF. This
can be further partitioned by the subregister number.

This is already mostly handled correctly for flags register, but lots
of places wanted to check the register number for equality with
BRW_ARF_ACCUMULATOR. If acc1 is ever specified, that won't work.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28281>
2024-03-21 15:12:54 -07:00
David Heidelberg
d8f53f698c util: move gen_zipped_file into generic util and rename to gen_zipped_xml_file
Make the filename more descriptive and since the file is used by
multiple drivers, move it into appropriate util/ directory.

Cosmetics:
 - use SPDX license tag
 - add newline before main function

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27804>
2024-03-21 20:48:41 +00:00
Echo J
16753bc2f1 nvk: Implement calibrated timestamps
This implementation is mostly a copy-paste from RADV

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28274>
2024-03-21 20:11:49 +00:00
Echo J
4b0ad410d0 nvk: Advertise VK_VALVE_mutable_descriptor_type
This missing extension looks bad when most of the other drivers
have it (so that's why I made this change)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28291>
2024-03-21 19:15:28 +00:00
Faith Ekstrand
359bb89302 nvk: Move the mutableDescriptorType enable
The EXT extension overrides the VALVE one so put it in the EXT section.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28291>
2024-03-21 19:15:28 +00:00
José Roberto de Souza
1bed037b88 iris: Remove i915_drm.h include from iris_indirect_gen.c
It don't use i915_drm.h no need to include.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28327>
2024-03-21 18:52:14 +00:00
José Roberto de Souza
50eceb1e33 iris: Move tiling_to_modifier() implementation to i915 folder
There is no tiling in Xe KMD uAPI.
With this one more i915_drm.h include can be removed.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28327>
2024-03-21 18:52:14 +00:00
Rohan Garg
cc570dbada isl: enable CCS for 3D surfaces on gen12.5 and above
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23632>
2024-03-21 18:28:27 +00:00
Rohan Garg
49ed35c08a anv: 3D surfaces have fewer layers for higher miplevels
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23632>
2024-03-21 18:28:27 +00:00
Rohan Garg
9628723943 anv,blorp: implement restrictions from WA 1406738321
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23632>
2024-03-21 18:28:27 +00:00
Valentine Burley
c83dcd4967 nvk: Trivially expose three VK_GOOGLE extensions
This patch exposes support for the following three extensions:

 * VK_GOOGLE_decorate_string
 * VK_GOOGLE_hlsl_functionality1
 * VK_GOOGLE_user_type

There's nothing for the driver to do; it's all handled in spirv_to_nir.

Signed-off-by: Valentine Burley <valentine.burley@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28155>
2024-03-21 18:10:04 +00:00
Robert Mader
b2719a73c1 crocus: Support offset query for multi-planar planes
Multi-planar planes can be imported from VA-API or V4L2. In this case we
would currently report wrong values for `gbm_bo_get_offset()`.

This does not fix any know visible bug, as crocus hardware usually does
not support muliti-planar planes in the display engine - in which case
the wrong values would make Mutter glitch. Lets report correct values
regardless.

While on it, also use the helper function for counting planes.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28225>
2024-03-21 17:49:31 +00:00
duncan.hopkins
899fcaf237 zink: Avoid issues when kopper tries using XCB WSI on Apple.
On macOS builds the code is tryng to use X11 and XCB code paths for WSI functions and structures,
i.e. `VkXcbSurfaceCreateInfoKHR` and `vkCreateXcbSurfaceKHR()`.
The MoltenVK implementation only supports `VkMacOSSurfaceCreateInfoMVK` and `vkCreateMacOSSurfaceMVK()`.
To get these working correctly Metal diusplay surfaces need to be setup, which xquarts does not expose.

Until this situation is resolved correctly the `VK_STRUCTURE_TYPE_XCB_SURFACE_CREATE_INFO_KHR` code paths has been
changed to return `VK_INCOMPLETE`. This allows them to run without asserting and terminating the runtime.
This allows for non-display applicaitons, like `glxinfo`, to run without terminating.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
d644b64ff2 zink: removed MESA_PRIM_QUADS from the supported PIPE_CAP_SUPPORTED_PRIM_MODES.
Vulkan does not support quads, removal of this type forces quads to be converted
in `primconvert_init_draw()`.

In cases where `screen->have_triangle_fans` excludes MESA_PRIM_TRIANGLE_FAN,
`u_index_generator()` is accessing a NULL entry in 'generate_quads'
for converting MESA_PRIM_TRIANGLE_FAN to MESA_PRIM_QUADS.
Which seems like an odd conversion to do (might be why it is missing).

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
7e1e0c6824 zink: stopped the use of VkFormatProperties3 if the reported API is less than 1.3 or VK_KHR_format_feature_flags2 not present.
The MoltenVK (time of writing) only implements Vulkan 1.2 APIs and no `VK_KHR_format_feature_flags2` device extension.
This means VkFormatProperties3 is not supported, and is left blank when used in `populate_format_props()`.
If non-1.3 is detected then the same values are read from the `VkFormatProperties2` `props` location.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
d0015ebbab zink: use portability EXT on Apple.
Vulkan behaviour has changed to require VK_INSTANCE_CREATE_ENUMERATE_PORTABILITY_BIT_KHR
and VK_KHR_portability_enumeration to be used on layered Vulkan implementations.
These are enbaled on macOS/Apple as MoltenVK is the only implmentation (time of writing)
and newer version require this.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
duncan.hopkins
32ac90d8c2 zink: Fixed header location and compiling issue with [[deprecated]] from newer MoltenVK versions.
From Vulkan 1.3.250 the MoltenVK include filenames changed.
Now include the newer 'MoltenVK/mvk_vulkan.h' instead of the older `MoltenVK/vk_mvk_moltenvk.h` headers.

From Vulkan 1.3.275 the MoltenVK include location changed.
The meson build options 'moltenvk-dir' now needs to point at the root of the Vulkan SDK install.
It will look for the presence of the older 'MoltenVK/include' loction and the newer 'macos/include' location.

Tested against Vulkan SDK versions: 1.3.250, 1.3.261, 1.3.268, 1.3.275.
Will not work compile with Vulkan 1.3.234 or earlier.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28259>
2024-03-21 17:22:34 +00:00
José Roberto de Souza
47bbd1c7ff intel/tools/error_decode: Parse HW context in Xe decoder
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27888>
2024-03-21 16:59:09 +00:00
José Roberto de Souza
ec3a41960b intel/tools/error_decode: Add function to print batch in Xe decoder
This will be useful to decode HW context in the next patch.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27888>
2024-03-21 16:59:09 +00:00
José Roberto de Souza
171eb89b75 intel/tools/error_decode: Fix parsing in Xe decoder
xe_topic can't be inside of the for loop otherwise it will be set to
TOPIC_INVALID at every iteration.

TOPIC_INVALID was added after it was reviewed by Lionel because CI
complained that xe_topic may be not initialized, turns out leaving it
not initialized was causing the xe_topic value to keep the value set
in the previous interation makeing the parser to work by luck.

Fixes: 90e38bbb3b ("intel/tools/error_decode: Parse Xe KMD error dump file")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27888>
2024-03-21 16:59:09 +00:00
Dylan Baker
477943cc9d meson: Allow building intel-clc for the host if it can be run
In what is probably the most common case  cross of compilation, x86_64
-> x86, it should be possible to build intel-clc for the host machine
and run it. Doing so simplifies the build by not needing to be able to
cross compile half of mesa, and should ease developer and distro strain
for building Intel drivers for x86.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28222>
2024-03-21 16:31:35 +00:00
Lionel Landwerlin
098136e52a anv: avoid partially compiled warning with GPL
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28318>
2024-03-21 16:09:54 +00:00
Vignesh Raman
3983ae89e9 Split debian-build-testing job
Split the build job from the shader-db tests so that the test
job can be rerun more reliably without hitting the timeout.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/9513
Signed-off-by: Vignesh Raman <vignesh.raman@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27507>
2024-03-21 13:26:20 +00:00
Mike Blumenkrantz
ee13512a62 zink: clamp swapchain renderarea instead of asserting
in a sequence like:
* resize A
* clear
* resize B
* clear
* resize C
* clear

for a swapchain resource, the geometry for a given op after the resize
may desync for the op with which it was executed, but this is fine
since the underlying swapchain object will have to be re-created anyway

fixes #10827

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
2024-03-21 13:05:04 +00:00
Mike Blumenkrantz
27f42a38aa zink: clamp present region size
it's illegal for these to exceed the size of the swapchain

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
2024-03-21 13:05:04 +00:00
Mike Blumenkrantz
1670c40557 zink: defer present barrier to flush if a clear is pending
this otherwise submits the swapchain with the wrong layout

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28214>
2024-03-21 13:05:04 +00:00
Christian Gmeiner
7e686fa417 etnaviv: isa: Define a dontcare bit in atomic instructions
Looks like it is the same as for ALU instructions: skpHp

This simplifies the special atomic handling a lot. Seen on blob
running a simple opencl shader on GC3000.

__kernel void kern(
   __global int *a,
   __global int *b,
   __global int *result)
{
   atomic_add(result, a[0]);
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28272>
2024-03-21 12:24:35 +00:00
Iago Toral Quiroga
83f53be8c7 broadcom/ci: add skips for unsupported features
Currently 92% of our Vulkan CI tests hit "Not Supported" test
cases, which is ridiculously high. Add a bunch of skips, some
of which include very large categories of tests of features we
already know we don't support, so we stop wasting so much time
skipping tests.

With this, we can also increase the fraction of tests we execute
for vulkan significantly, while still keeping job run times
under control.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28264>
2024-03-21 11:47:50 +00:00
Eric Engestrom
795046a8d4 v3dv/ci: update expectations
A big chunk of the new flakes and timeouts are caused by enabling new
tests in f977e4d4f5 ("v3dv: Enable
EXT_swapchain_maintenance1").

I'm not quite sure what happened with
`dEQP-VK.wsi.wayland.swapchain.simulate_oom.*` but now at least half of
them are flaky on rpi4 (between Skip and Crash), so moving the whole
block to flakes. On rpi5 I haven't seen them flake yet so tentatively
removing them entirely, but there's a good chance the issue is common
and they'll have to be put into flakes on rpi5 at some point as well.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28316>
2024-03-21 11:20:18 +00:00
Samuel Pitoiset
4b065fe863 zink/ci: update CI lists
This seems to have been fixed quite recently.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28315>
2024-03-21 10:38:18 +01:00
Christian Gmeiner
e0ca29e7a3 isaspec: deocde: Remove generic functions from public interface
This will switch everyone to the isa specific functions.

Fixes the output of etnaviv's pre_instr_cb callback if
freedreno and etnaviv are build at the same time.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
3f2295d99b isaspec: decode: Add libisaspec
Create a static library that just contains isa_print(..). We
need to do this step to make lto happy.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
878fa2032e isaspec: deocde: Make isa_decode_field(..) private
Without this change the isa_decode_field(..) uses the wrong bitmask_t
type (freedreno: array with 2 elements, etnaviv: array with 4 elements)
and weird things happens.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
872f714e32 isaspec: deocde: Make isa_bitset arrays static
Without this commit etnaviv_isa_disasm(..) will call into
find_field(..) and use the bitsets are the one from freedreno.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
1196b82815 etnaviv: isa: Rework meson dependency for libetnaviv_decode
Any component that links against libetnaviv_decode should not need to
take care if the generated isa files exists.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
f396899983 freedreno/isa: Rework meson dependency for libir3decode
Any component that links against libir3decode should not need to
take care if the generated isa files exists.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
505ec13f87 isaspec: decode: Make isa_decode_bitset(..) private
Fixes lto issues later in the series.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
77872bec95 isaspec: decode: Add isa specific functions
In the end we want to only the specific functions and remove
the generic ones from the public interface.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
16e8a3548f isaspec: deocde: Hide all the internals ISA details
There are no users of these defines, structs and functions
outside of the generated isa.c file. I left the empty header
as it will be used in later commits.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:18 +00:00
Christian Gmeiner
08e899852b isaspec: Remove not used isa_decode_hook
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28176>
2024-03-21 07:51:17 +00:00
Marek Olšák
651191801a gallium: increase the size of pipe_box y, height fields to allow bigger textures
and reorder the fields to pack them better

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27953>
2024-03-21 03:33:39 +00:00
Marek Olšák
bfdbfd6ade gallium: use u_box_3d to initialize pipe_box instead of non-designated initializers
This is the original utility for initializing pipe_box.
It prevents breakage when pipe_box fields are reordered.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27953>
2024-03-21 03:33:39 +00:00