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Author SHA1 Message Date
Samuel Pitoiset
48b4a43e8f amd,radv,radeonsi: add ac_emit_cp_set_predication() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
 2025-10-16 06:31:36 +00:00
Rhys Perry
3e9921f52e radv: only call radv_should_use_wgp_mode() once 
This will let the compiler choose between CU and WGP mode.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37791>
 2025-10-15 13:37:48 +01:00
Daniel Schürmann
b2c44e3a65 amd: change radeon_info::lds_size_per_workgroup for GFX10+ to 64KB
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Even though in WGP-mode, there is a total of 128KB LDS, a single workgroup
can access at most 64KB.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37577>
 2025-10-15 11:20:09 +00:00
Daniel Schürmann
eecd1c020d amd: keep ac_shader_config::lds_size unaligned 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37577>
 2025-10-15 11:20:09 +00:00
Daniel Schürmann
f99eba729d amd/common: remove radeon_info::lds_alloc_granularity and radeon_info::lds_encode_granularity 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37577>
 2025-10-15 11:20:08 +00:00
Daniel Schürmann
6fd5766620 amd: add and use utility functions for LDS size encoding 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37577>
 2025-10-15 11:20:08 +00:00
Daniel Schürmann
b651234414 amd: change ac_shader_config::lds_size to bytes 
We still keep it aligned to allocation granularity.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37577>
 2025-10-15 11:20:07 +00:00
David Rosca
282e8285f1 ac/surface: Limit video modifiers to 64K_S also for VCN 2.2 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14032
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37819>
 2025-10-15 10:24:29 +00:00
Samuel Pitoiset
88f53906d8 amd,radv,radeonsi: add ac_emit_cp_pfp_sync_me() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:25 +00:00
Samuel Pitoiset
7ead034a06 amd,radv,radeonsi: add ac_emit_cp_copy_data() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:25 +00:00
Samuel Pitoiset
0e358cec52 amd,radv,radeonsi: add ac_emit_cp_release_mem_pws() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:24 +00:00
Samuel Pitoiset
c45035ceb4 amd,radv,radeonsi: add ac_emit_cp_acquire_mem_pws() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:23 +00:00
Samuel Pitoiset
6329e282b8 amd,radv,radeonsi: add ac_emit_cp_wait_mem() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:23 +00:00
Samuel Pitoiset
82cbfc964a amd,radv: add ac_emit_write_data_imm() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:20 +00:00
Samuel Pitoiset
ac262c351f amd,radv: add ac_emit_cond_exec() 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37813>
 2025-10-15 07:35:20 +00:00
David Rosca
3e458d06b8 radeonsi/vcn: Support BT2020 matrix with EFC 
Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37058>
 2025-10-15 06:06:44 +00:00
Daniel Schürmann
d0b87a0d5f ac/nir_flag_smem_for_loads: call divergence analysis internally
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Also don't flag more SMEM instructions (in ACO) after the last
call to ac_nir_lower_mem_access_bit_sizes().

Totals from 75 (0.09% of 79839) affected shaders: (Navi48)

Instrs: 191246 -> 189960 (-0.67%)
CodeSize: 996840 -> 985976 (-1.09%)
Latency: 3066184 -> 2945500 (-3.94%)
InvThroughput: 355373 -> 353106 (-0.64%); split: -0.66%, +0.02%
SClause: 4848 -> 4699 (-3.07%)
Copies: 13827 -> 13925 (+0.71%); split: -0.07%, +0.78%
Branches: 5176 -> 5003 (-3.34%)
PreSGPRs: 6222 -> 6272 (+0.80%)
VALU: 108934 -> 108993 (+0.05%); split: -0.00%, +0.06%
SALU: 31679 -> 31210 (-1.48%); split: -1.51%, +0.03%
SMEM: 7158 -> 6739 (-5.85%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37843>
 2025-10-14 16:33:12 +00:00
Daniel Schürmann
9b1a635bb3 amd/common: merge radv_nir_opt_access_speculate() into ac_nir_flag_smem_for_loads() 
One shader is negatively affected, but we save 2 entire iterations over every shader.
This effect is also mitigated with the next commits.

Totals from 1 (0.00% of 79839) affected shaders: (Navi48)

Instrs: 947 -> 958 (+1.16%)
CodeSize: 4728 -> 4732 (+0.08%)
Latency: 20678 -> 20723 (+0.22%)
InvThroughput: 2697 -> 2698 (+0.04%)
SClause: 26 -> 27 (+3.85%)
Copies: 139 -> 145 (+4.32%)
Branches: 46 -> 47 (+2.17%)
VALU: 460 -> 463 (+0.65%)
SALU: 201 -> 204 (+1.49%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37843>
 2025-10-14 16:33:12 +00:00
Daniel Schürmann
8ff44f17ef amd/lower_mem_access_bit_sizes: also use SMEM for subdword loads 
We can simply extract from the loaded dwords as per
nir_lower_mem_access_bit_sizes() lowering.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37843>
 2025-10-14 16:33:11 +00:00
Daniel Schürmann
fbf0399517 amd/lower_mem_access_bit_sizes: lower all SMEM instructions to supported sizes 
This creates more SMEM instruction, mostly because vec3 64bit are being split
instead of overfetched.

Totals from 442 (0.55% of 79839) affected shaders: (Navi48)

Instrs: 288998 -> 289469 (+0.16%); split: -0.04%, +0.21%
CodeSize: 1538212 -> 1541460 (+0.21%); split: -0.03%, +0.24%
Latency: 3010072 -> 3009373 (-0.02%); split: -0.04%, +0.01%
InvThroughput: 885572 -> 885564 (-0.00%); split: -0.00%, +0.00%
VClause: 6900 -> 6885 (-0.22%); split: -0.28%, +0.06%
SClause: 4457 -> 4469 (+0.27%); split: -0.18%, +0.45%
VALU: 162473 -> 162469 (-0.00%)
SALU: 42871 -> 42855 (-0.04%); split: -0.05%, +0.01%
SMEM: 6893 -> 7239 (+5.02%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37843>
 2025-10-14 16:33:11 +00:00
Samuel Pitoiset
bc32286e5b radv: declare a new user SGPR for dynamic descriptors 
To move them out of push constants.

fossils-db (GFX1201):
Totals from 20700 (25.99% of 79646) affected shaders:
Instrs: 14375624 -> 14370051 (-0.04%); split: -0.07%, +0.03%
CodeSize: 76746128 -> 76723772 (-0.03%); split: -0.05%, +0.02%
Latency: 74103586 -> 74113651 (+0.01%); split: -0.01%, +0.02%
InvThroughput: 11908817 -> 11908798 (-0.00%); split: -0.00%, +0.00%
VClause: 249605 -> 249607 (+0.00%); split: -0.00%, +0.00%
SClause: 337914 -> 337772 (-0.04%); split: -0.08%, +0.04%
Copies: 843585 -> 839233 (-0.52%); split: -0.62%, +0.10%
PreSGPRs: 836283 -> 837260 (+0.12%)
SALU: 1790713 -> 1786374 (-0.24%); split: -0.29%, +0.05%

Co-authored-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37768>
 2025-10-14 15:34:43 +00:00
David Rosca
c941e57d74 ac/gfx10_format_table: Use new names for 422 subsampled formats 
Fixes: f20ee2806e ("util/format: Add subsampling info to our YUV-as-RGB format names")
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37838>
 2025-10-14 09:33:28 +00:00
Georg Lehmann
e26a8be7af ac/nir: enable nir atomic load/store opts 
Foz-DB GFX1201:
Totals from 4 (0.00% of 80287) affected shaders:
Instrs: 2928 -> 2920 (-0.27%); split: -0.31%, +0.03%
CodeSize: 15424 -> 15392 (-0.21%); split: -0.23%, +0.03%
Latency: 835578 -> 823220 (-1.48%)
InvThroughput: 3307941 -> 3258515 (-1.49%)
Copies: 459 -> 447 (-2.61%)
VALU: 1297 -> 1291 (-0.46%)
SALU: 595 -> 589 (-1.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37822>
 2025-10-14 06:24:17 +00:00
Samuel Pitoiset
ef900e93fc ac/surface: fix host image copies with stencil-only 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
9a7f1401d8 ac/surface: fix host image copies with 96-bits formats 
Fixes dEQP-VK.image.host_image_copy.simple.r32g32b32_* with
RADV_PERFTEST=hic on RADV.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37748>
 2025-10-10 13:46:51 +00:00
Samuel Pitoiset
aeec53f020 radv,radeonsi: use new ac_cmdbuf macros 
But keep them behind existing macros for consistency until all macros
are moved to common code.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:15 +00:00
Samuel Pitoiset
902f5a8618 radv: replace radeon_cmdbuf by ac_cmdbuf completely 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:15 +00:00
Samuel Pitoiset
9ff4750eaf ac/cmdbuf: introduce ac_cmdbuf 
This will be shared by both drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset
a7ae26c96c ac/sqtt: use void pointers for start/stop CS 
Similar to BOs which are different structs between drivers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:14 +00:00
Samuel Pitoiset
12cccb2f75 radv: remove useless radeon_cmdbuf forwarded declaration 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36292>
 2025-10-08 18:00:13 +00:00
Marek Olšák
3fe651f607 nir: remove load_smem_amd 
replaced by load_global_amd + ACCESS_SMEM_AMD

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:11 +00:00
Daniel Schürmann
3ae2f12eb4 ac/nir: switch load_smem_amd to use load_global 
Totals from 24920 (31.21% of 79839) affected shaders: (Navi48)

Instrs: 22044185 -> 22413945 (+1.68%); split: -0.01%, +1.68%
CodeSize: 117211728 -> 118623656 (+1.20%); split: -0.01%, +1.21%
VGPRs: 1199008 -> 1198948 (-0.01%)
SpillSGPRs: 7421 -> 7365 (-0.75%); split: -0.78%, +0.03%
SpillVGPRs: 2177 -> 2184 (+0.32%); split: -0.09%, +0.41%
Scratch: 7037952 -> 7038208 (+0.00%)
Latency: 155140452 -> 155530877 (+0.25%); split: -0.02%, +0.27%
InvThroughput: 23601713 -> 23634131 (+0.14%); split: -0.01%, +0.15%
VClause: 458456 -> 458575 (+0.03%); split: -0.09%, +0.11%
SClause: 651928 -> 649405 (-0.39%); split: -1.26%, +0.87%
Copies: 1681110 -> 1677057 (-0.24%); split: -0.42%, +0.17%
Branches: 515419 -> 515322 (-0.02%); split: -0.02%, +0.00%
PreSGPRs: 992903 -> 990545 (-0.24%); split: -0.24%, +0.00%
VALU: 11971995 -> 11967962 (-0.03%); split: -0.04%, +0.00%
SALU: 3247576 -> 3476720 (+7.06%); split: -0.03%, +7.08%
VMEM: 821046 -> 821056 (+0.00%); split: -0.00%, +0.00%
SMEM: 988476 -> 988779 (+0.03%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:54:11 +00:00
Daniel Schürmann
fdd6bdf03d ac/nir_lower_global_access: don't assume pack_64_2x32 is the same as u2u64 
It might also be the expanded base address.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:53:58 +00:00
Daniel Schürmann
0209065229 ac/nir_lower_global_access: require no_unsigned wrap when extracting from 32-bit additions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36936>
 2025-10-08 08:53:58 +00:00
Rhys Perry
20af16b4d8 aco: use MTBUF for 64-bit atomic load/store
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
A 64-bit atomic load/store should be considered entirely out-of-bounds if
any part of it is out-of-bounds. Since we implemented these as 32-bit vec2
load/store, it would have been possible for the first half to be in-bounds
while the second half is out-of-bounds.

From 9.6.1. Robust Buffer Access of Vulkan 1.4.324 specification:
> Any non-atomic access to a uniform, storage, uniform texel, or storage
> texel buffer wider than 32-bits may be treated as multiple 32-bit
> accesses that are separately bounds checked.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36602>
 2025-10-07 17:41:31 +00:00
Timur Kristóf
92ba76710d ac/gpu_info: Add can_chain_ib2 field to ac_gpu_info 
GFX6 supports IB2, but not chaining inside IB2.
It only supports chaining in IB1.
See waCpIb2ChainingUnsupported in PAL.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37280>
 2025-10-07 15:49:01 +00:00
Georg Lehmann
84f26ed117 nir: optimize atomic isub if supported 
Foz-DB Navi48:
Totals from 1 (0.00% of 80287) affected shaders:
Instrs: 1641 -> 1637 (-0.24%)
CodeSize: 8472 -> 8456 (-0.19%)
Latency: 19132 -> 19131 (-0.01%)
InvThroughput: 9566 -> 9565 (-0.01%)
Copies: 126 -> 125 (-0.79%)
VALU: 565 -> 563 (-0.35%)
SALU: 439 -> 438 (-0.23%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37702>
 2025-10-07 14:07:56 +00:00
Yinjie Yao
f0f95a9ae3 ac/parse_ib: Update vcn ib parser to include missing commands 
Signed-off-by: Yinjie Yao <yinjie.yao@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: David Rosca <david.rosca@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37672>
 2025-10-03 14:44:07 +00:00
Daniel Schürmann
0e3bc3d8c0 nir/opt_offsets: call allow_offset_wrap() for try_fold_shared2()
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
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This prevents applying wrapping offsets on GFX6.

Fixes: e1a692f74b ('nir/opt_offsets: allow for unsigned wraps when folding load/store_shared2_amd offsets')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37667>
 2025-10-03 07:54:12 +00:00
Daniel Schürmann
93ce29c42e amd: don't allow unsigned wraps for shared memory offsets on GFX6 
Fixes: 10266e7b21 ('radv: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets')
Fixes: dd68825feb ('radeonsi: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37667>
 2025-10-03 07:54:12 +00:00
Vitaliy Triang3l Kuzmin
dea20be1b3 ac: Enable HTILE TC Z clear value bug workaround on GFX1013
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
Details 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33962>
 2025-10-02 08:29:50 +00:00
Vitaliy Triang3l Kuzmin
4e3a5f60e1 radv,ac: Split has_tc_compat_zrange_bug into Z and ZS, document it 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33962>
 2025-10-02 08:29:49 +00:00
Vitaliy Triang3l Kuzmin
5243f292ef radv,ac: GFX10 depth/stencil HTILE mipmap bug info variable 
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33962>
 2025-10-02 08:29:48 +00:00
Timur Kristóf
d3579190d6 ac/nir/ngg: Fix scalarized mesh primitive indices
Some checks are pending
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macOS-CI / macOS-CI (xlib) (push) Waiting to run
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Take the write_mask into account when storing primitive indices,
otherwise they will end up being stored in the wrong place.

Fixes: 8e24d3426d ("ac/nir/ngg: Refactor MS primitive indices for scalarized IO.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37610>
 2025-09-29 08:07:54 +00:00
Timur Kristóf
3dc9c1a91e ac/nir/ngg: Remove dead code for 64-bit mesh shader variables 
We already lower all 64-bit I/O to 32-bit before this pass,
and the rest of the code here already asserts that I/O variables
must be 32-bit or smaller.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37610>
 2025-09-29 08:07:54 +00:00
Daniel Schürmann
10266e7b21 radv: allow for unsigned wraps for shared memory intrinsics in nir_opt_offsets 
Totals from 76 (0.10% of 79839) affected shaders: (Navi48)

Instrs: 237450 -> 237323 (-0.05%); split: -0.05%, +0.00%
CodeSize: 1276732 -> 1275824 (-0.07%); split: -0.07%, +0.00%
Latency: 1123467 -> 1123387 (-0.01%); split: -0.01%, +0.01%
InvThroughput: 364942 -> 364738 (-0.06%); split: -0.06%, +0.00%
Copies: 20654 -> 20636 (-0.09%); split: -0.09%, +0.00%
Branches: 7326 -> 7327 (+0.01%)
PreSGPRs: 5197 -> 5195 (-0.04%)
PreVGPRs: 3395 -> 3396 (+0.03%)
VALU: 96134 -> 96034 (-0.10%)
SALU: 48059 -> 48041 (-0.04%); split: -0.04%, +0.00%
VOPD: 10 -> 8 (-20.00%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37453>
 2025-09-24 14:28:24 +00:00
Rhys Perry
92a2ab8b64 ac/nir: fix progress reporting in ac_nir_lower_tex 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35069>
 2025-09-24 08:20:27 +00:00
Georg Lehmann
714a149396 nir: remove unsigned upper bound config 
All config information is now either in nir->info or nir->options.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37361>
 2025-09-16 09:24:04 +00:00
Qiang Yu
310cfda034 ac/surface: add ac_compute_surface_modifier 
Used by radeonsi to export existing texture modifier.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
 2025-09-15 09:39:19 +00:00
Qiang Yu
98cd68ec05 ac/surface: add radeonsi exported modifiers to supported list 
radeonsi will export texture with these modifiers.

piglit tests:
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-export-tex
spec@ext_image_dma_buf_import@ext_image_dma_buf_import-tex-modifier

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31658>
 2025-09-15 09:39:19 +00:00