Commit graph

105958 commits

Author SHA1 Message Date
Marek Olšák
442dae2693 radeonsi: clean up primitive binning enablement
no change in behavior.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-28 20:20:27 -05:00
Dave Airlie
8eb8be3f54 virgl: fix undefined shift to use unsigned.
Ported from virglrenderer.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-11-29 09:09:31 +10:00
Dave Airlie
2ddd44d941 r600: make suballocator 256-bytes align
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108311
Cc: <mesa-stable@lists.freedesktop.org>
2018-11-29 09:09:02 +10:00
Kenneth Graunke
f11780779f intel/compiler: Use nir's info when checking uses_streams.
Vulkan and Gallium don't use Mesa's gl_program data structure, so they
can't poke at 'prog'.  But we can simply use the copy of the shader info
stored with the NIR shader, which is guaranteed to exist.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-11-28 13:35:29 -08:00
Jason Ekstrand
199a0353d6 nir/derefs: Add a nir_derefs_do_not_alias enum value
This makes some of the code more clear.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com>
2018-11-28 14:29:25 -06:00
Gurchetan Singh
eb44c36cf1 egl: add missing #include <stddef.h> in egldevice.h
Otherwise, I get this error:

main/egldevice.h:54:13: error: ‘NULL’ undeclared (first use in this function)
       dev = NULL;
             ^~~~
with this config:

./autogen.sh --enable-gles1 --enable-gles2 --with-platforms='surfaceless' --disable-glx
             --with-dri-drivers="i965" --with-gallium-drivers="" --enable-gbm

v3: Use stddef.h (Matt)
v4: Modify commit message (Eric)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-28 11:22:47 -08:00
Matt Turner
2d48d5116b gallivm: Use nextafterf(0.5, 0.0) as rounding constant
The common truncf(x + 0.5) fails for the floating-point value just less
than 0.5 (nextafterf(0.5, 0.0)). nextafterf(0.5, 0.0) + 0.5, after
rounding is 1.0, thus truncf does not produce the desired value.

The solution is to add nextafterf(0.5, 0.0) instead of 0.5 before
truncating. This works for all values.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-11-28 11:22:47 -08:00
Juan A. Suarez Romero
e2ad94d928 docs: update calendar, add news item and link release notes for 18.2.6
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2018-11-28 19:20:09 +01:00
Juan A. Suarez Romero
a53a280479 docs: add sha256 checksums for 18.2.6
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit cfd1f8b92c)
2018-11-28 19:20:09 +01:00
Juan A. Suarez Romero
f6ab6e2867 docs: add release notes for 18.2.6
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 3e741344d7)
2018-11-28 19:20:09 +01:00
Nicolai Hähnle
c02390f8fc egl/wayland: rather obvious build fix
Fixes: ce74a7bb8d ("egl/wayland: plug memory leak in drm_handle_device()")
Fixes: c59d3aa4b9 ("egl/wayland: bail out when drmGetMagic fails")
2018-11-28 18:30:36 +01:00
Nicolai Hähnle
eb94b6bd5c winsys/amdgpu: explicitly declare whether buffer_map is permanent or not
Introduce a new driver-private transfer flag RADEON_TRANSFER_TEMPORARY
that specifies whether the caller will use buffer_unmap or not. The
default behavior is set to permanent maps, because that's what drivers
do for Gallium buffer maps.

This should eliminate the need for hacks in libdrm. Assertions are added
to catch when the buffer_unmap calls don't match the (temporary)
buffer_map calls.

I did my best to update r600 for consistency (r300 needs no changes
because it never calls buffer_unmap), even though the radeon winsys
ignores the new flag.

As an added bonus, this should actually improve the performance of
the normal fast path, because we no longer call into libdrm at all
after the first map, and there's one less atomic in the winsys itself
(there are now no atomics left in the UNSYNCHRONIZED fast path).

Cc: Leo Liu <leo.liu@amd.com>
v2:
- remove comment about visible VRAM (Marek)
- don't rely on amdgpu_bo_cpu_map doing an atomic write
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-11-28 18:24:14 +01:00
Nicolai Hähnle
35eb81987c winsys/amdgpu: add amdgpu_winsys_bo::lock
We'll use it in the upcoming mapping change. Sparse buffers have always
had one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-11-28 18:23:29 +01:00
Eric Engestrom
e0f1f74eda vulkan/wsi: fix s/,/;/ typo
Fixes: 59e58c348e "vulkan/wsi: Only wait on semaphores on the first swapchain"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-11-28 16:44:01 +00:00
Emil Velikov
ce74a7bb8d egl/wayland: plug memory leak in drm_handle_device()
As we fail to open the node, we leak the node/device name.

v2: Log and then free() (Eric)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-28 16:12:12 +00:00
Emil Velikov
c59d3aa4b9 egl/wayland: bail out when drmGetMagic fails
Currently as the function fails, we pass uninitialized data to the
authentication function. Stop doing that and print an warning when
the function fails.

v2: Plug memory leak in error path (Eric)

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-28 16:11:22 +00:00
Eric Engestrom
9575cd2893 wsi/display: fix mem leak when freeing swapchains
Fixes: da997ebec9 "vulkan: Add KHR_display extension using DRM [v10]"
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
2018-11-28 12:09:54 +00:00
Gert Wollny
f08d107054 i965: Set the FBO error state INCOMPLETE_ATTACHMENT only for SRGB_R8
Originally the driver reported GL_FRAMEBUFFER_UNSUPPORTED in all cases,
adding more specific error messages was not correct and broke many tests.
Mostly revert this and only report GL_FRAMEBUFFER_INCOMPLETE_ATTACHMENT
for MESA_FORMAT_R_SRGB8.

Fixes: ebcde34545
  i965: be more specific about FBO completeness errors

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108805

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-28 10:12:47 +01:00
Gert Wollny
d8bb88d0b4 i965: Explicitely handle swizzles for MESA_FORMAT_R_SRGB8
The format is emulated by using ISL_FORMAT_L8_SRGB, therefore we need to
force swizzles for the GBA channels. However, doing this only based on the
data type GL_RED breaks other formats, therefore, test specifically for the
format.

Fixes: c5363869d4
  i965: Force zero swizzles for unused components in GL_RED and GL_RG
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-28 10:07:02 +01:00
Gert Wollny
091295d7cb virgl: Don't try handling server fences when they are not supported
vtest doesn't implement the according API and would segfault:

Program received signal SIGSEGV, Segmentation fault.
  #0  0x0000000000000000 in ?? ()
  #1  in virgl_fence_server_sync  at
       src/gallium/drivers/virgl/virgl_context.c:1049
  #2  in st_server_wait_sync  at
       src/mesa/state_tracker/st_cb_syncobj.c:155

so just don't do the call when the function pointers are not set.

Fixes dEQP:
  dEQP-GLES3.functional.fence_sync.wait_sync_smalldraw
  dEQP-GLES3.functional.fence_sync.wait_sync_largedraw

Fixes: d1a1c21e76
  virgl: native fence fd support

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
2018-11-28 10:02:31 +01:00
Gert Wollny
073fdd7382 virgl,vtest: Initialize return value
Avoids:
Conditional jump or move depends on uninitialised value(s)
  at 0x9E2B39F: virgl_vtest_winsys_resource_cache_create (virgl_vtest_winsys.c:379)
  by 0x9E2725F: virgl_buffer_create (virgl_buffer.c:169)
  by 0x9E246D5: virgl_resource_create (virgl_resource.c:60)
  by 0xA0C1B9F: bufferobj_data (st_cb_bufferobjects.c:344)
  by 0xA0C1B9F: st_bufferobj_data (st_cb_bufferobjects.c:390)
  by 0x9F4ACE3: vbo_use_buffer_objects (vbo_exec_api.c:1136)
  by 0xA0C68C3: st_create_context_priv (st_context.c:416)
  by 0xA0C707A: st_create_context (st_context.c:598)
  by 0x9F81C6B: st_api_create_context (st_manager.c:918)
  by 0x9BBE591: dri_create_context (dri_context.c:161)
  by 0x9BB6931: driCreateContextAttribs (dri_util.c:473)
  by 0x4E97A44: drisw_create_context_attribs (drisw_glx.c:630)
  by 0x4E7C591: glXCreateContextAttribsARB (create_context.c:78)
Uninitialised value was created by a stack allocation
  at 0x9E2B249: virgl_vtest_winsys_resource_cache_create (virgl_vtest_winsys.c:342)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Robert Foss <robert.foss@collabora.com>
2018-11-28 10:02:31 +01:00
Iago Toral Quiroga
e55cbf26ea intel/compiler: fix register allocation in opt_peephole_sel
This wasn't handling 64-bit cases properly. Found by inspection.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2018-11-28 08:28:27 +01:00
Matt Turner
6f737b9207 glsl: Remove unused member variable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-27 22:29:53 -08:00
Matt Turner
1a210268b8 nir: Call fflush() at the end of nir_print_shader()
We normally call with stderr which is unbuffered, so this won't affect
that, but it does let me call nir_print_shader(nir, fopen("log", "w+"))
from gdb and actually get the whole shader in my file.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2018-11-27 22:29:53 -08:00
Eric Anholt
e113b21cb7 v3d: Add renderonly support.
I've been using this with the kmsro series to test v3d on VKMS without my
old KMS hack in the v3d kernel driver.  KMSRO still needs some cleanup,
but v3d RO support seems reasonable.
2018-11-27 15:03:02 -08:00
Eric Anholt
55edafa73e gallium: Remove unused variable in u_tests.
Fixes: 0d17b685b1 ("gallium/u_tests: add a compute shader test that clears an image")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-11-27 15:02:57 -08:00
Bas Nieuwenhuizen
6569644bb6 radv: Align large buffers to the fragment size.
Improves performance in Talos by about 15% (and significant improvements
in RotR and possibly other but did not bench with final patch) on
kernel 4.19 and earlier.

On 4.20+ a similar effect comes from

433ca054949a "drm/amdgpu: try allocating VRAM as power of two"

v2: Do not impact the alignment of the physical memory.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
CC: <mesa-stable@lists.freedesktop.org>
2018-11-27 22:17:42 +01:00
Hyunjun Ko
76945e4140 freedreno: implements get_sample_position
Since 1285f71d3e landed, it needs to provide apps with proper sample
position for MSAA.

Currently no way to query this to hw, these are taken from blob driver.

Fixes: dEQP-GLES31.functional.texture.multisample.samples_#.sample_position
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Rob Clark
5973a4d0b7 freedreno/a3xx: also set FSSUPERTHREADENABLE
We set equiv bit in SP_FS_CTRL_REG0.  Somehow the hw doesn't hang with
this mismatched config, but does run slower.  It is faster with either
neither bit set, or both bits set, but both is the fastest of the three
configurations.  Worth a bit over 10% gain in glmark2.

Spotted-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
e68cd91251 freedreno: use MSM_BO_SCANOUT with scanout buffers
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
2018-11-27 15:44:03 -05:00
Jonathan Marek
3ed4aad524 freedreno: use GENERIC instead of TEXCOORD for blit program
blip_fp uses GENERIC as input, so blit_vp should match for linking

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
3a273a4abc freedreno: a2xx texture update
Adds all missing texture related logic. For everything to work it also
needs changes to ir2/fd2_program, which are part of the ir2 update patch.

Note: it needs rnndb update

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
[remove stray patch]
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
4887aba638 freedreno/a2xx: Compute depth base in gmem correctly
Note: it needs rnndb update

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
e7114575f7 freedreno/a2xx: set VIZ_QUERY_ID on a20x
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
a50b8a0152 freedreno: add missing a20x ids
200: 256KiB GMEM A200 (imx53)
201: 128KiB GMEM A200 (imx51)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
4e6ee033ff freedreno/a2xx: fix POINT_MINMAX_MAX overflow
As it stands, it overflows to zero.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:03 -05:00
Jonathan Marek
78fede86d9 freedreno: a2xx: fd2_draw update
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Jonathan Marek
3e7186d472 nir: add fceil lowering
lowers ceil(x) as -floor(-x)

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
11593f9041 freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
d47d77d49d freedreno/a6xx: set guardband clip
On older gens, the CLIP_ADJ bitfields were actually 3.6 fixed point.
Which might make more sense.  Although this formula comes up with values
pretty close to what blob does for various viewport sizes (for at least
a5xx and a6xx), and seems to work.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
2773919f06 freedreno/a6xx: disable LRZ for z32
f6131d4ec7 had the side effect of enabling LRZ w/ 32b depth buffers.
But there are some bugs with this, which aren't fully understood yet,
so for now just skip LRZ w/ z32..

Fixes: f6131d4ec7 freedreno/a6xx: Clear z32 and separate stencil with blitter
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Kristian H. Kristensen
9595be67a9 freedreno/a6xx: Clear gmem buffers at flush time
We generate an IB to clear the gmem at flush time and jump to it
before rendering each tile. This lets us get rid of the command stream
patching for gmem offsets.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Kristian H. Kristensen
b5a9bb28c6 freedreno/a6xx: Move resolve blits to an IB
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Kristian H. Kristensen
5f068cf3b0 freedreno/a6xx: Move restore blits to IB
Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
09300bbe03 mesa/st: better colormask check for clear fallback
For RGB surfaces (for example) we don't really care that the colormask
is 0x7 instead of 0xf.  This should not trigger clear_with_quad()
slowpath.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-11-27 15:44:02 -05:00
Rob Clark
65cee01430 mesa/st: swap order of clear() and clear_with_quad()
If we can't clear all the buffers with pctx->clear() (say, for example,
because of ColorMask), push the buffers we *can* clear with pctx->clear()
first.  Tilers want to see clears coming before draws to enable fast-
paths, and clearing one of the attachments with a quad-draw first
confuses that logic.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-27 15:44:02 -05:00
Rob Clark
aa0fed10d3 freedreno: move ir3 to common location
Move (most of) the ir3 compiler to src/freedreno/ir3 so that it can be
re-used by some future vulkan driver.  The parts that are gallium
specific have been refactored out and remain in the gallium driver.

Getting the move done now so that it can happen before further
refactoring to support a6xx specific instructions.

NOTE also removes ir3_cmdline compiler tool from autotools build since
that was easier than fixing it and I normally use meson build.  Waiting
patiently for the day that we can remove *everything* from the autotools
build.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
556eec249d freedreno/ir3: remove u_inlines usage
Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
312eae45a3 freedreno/ir3: split up ir3_shader
Split the parts that are gallium specific into ir3_gallium so the rest
can move to a common location outside of gallium.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00
Rob Clark
ea4cbf601d freedreno/ir3: remove pipe_stream_output_info dependency
A bit annoying to have to copy into our own struct.  But this is
something the compiler really needs to know, at least on earlier
generations where streamout is implemented in shader.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2018-11-27 15:44:02 -05:00