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radv/video: Support UVD decode on hawaii and older

Browse source 
H264 requires extra allocation in DPB. Use helper function
to get the required size, same as we do for encode.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39627>
This commit is contained in:
David Rosca 2026-02-09 11:16:47 +01:00 • committed by Marge Bot
parent 24c74f522c
commit 5d4f977573
5 changed files with 33 additions and 7 deletions
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4
src/amd/vulkan/radv_image.c
View file

@ -1233,8 +1233,8 @@ radv_image_create_layout(struct radv_device *device, struct radv_image_create_in
}
if (radv_has_uvd(pdev) && image->vk.usage & VK_IMAGE_USAGE_VIDEO_DECODE_DPB_BIT_KHR) {
/* UVD and kernel demand a full DPB allocation. */
image_info.array_size = MIN2(16, image_info.array_size);
radv_video_get_uvd_dpb_image(pdev, profile_list, image);
return VK_SUCCESS;
}
if (image->vk.usage & VK_IMAGE_USAGE_VIDEO_ENCODE_DPB_BIT_KHR) {

2
src/amd/vulkan/radv_physical_device.c
View file

@ -730,7 +730,7 @@ radv_physical_device_get_supported_extensions(const struct radv_physical_device
VIDEO_CODEC_AV1DEC && pdev->video_decode_enabled),
.KHR_video_decode_queue = pdev->video_decode_enabled,
.KHR_video_decode_h264 = VIDEO_CODEC_H264DEC && pdev->video_decode_enabled,
.KHR_video_decode_h265 = VIDEO_CODEC_H265DEC && pdev->video_decode_enabled,
.KHR_video_decode_h265 = pdev->info.family >= CHIP_TONGA && VIDEO_CODEC_H265DEC && pdev->video_decode_enabled,
.KHR_video_decode_vp9 =
(radv_video_decode_vp9_supported(pdev) && VIDEO_CODEC_VP9DEC && pdev->video_decode_enabled),
.KHR_video_encode_h264 = VIDEO_CODEC_H264ENC && pdev->video_encode_enabled,

4
src/amd/vulkan/radv_physical_device.h
View file

@ -260,10 +260,6 @@ radv_has_pops(const struct radv_physical_device *pdev)
static inline bool
radv_has_uvd(struct radv_physical_device *pdev)
{
enum radeon_family family = pdev->info.family;
/* Only support UVD on TONGA+ */
if (family < CHIP_TONGA)
return false;
return pdev->info.ip[AMD_IP_UVD].num_queues > 0;
}

28
src/amd/vulkan/radv_video.c
View file

@ -2234,6 +2234,34 @@ radv_video_get_profile_alignments(struct radv_physical_device *pdev, const VkVid
*height_align_out = MAX2(*height_align_out, db_alignment);
}
void
radv_video_get_uvd_dpb_image(struct radv_physical_device *pdev, const struct VkVideoProfileListInfoKHR *profile_list,
struct radv_image *image)
{
const bool is_10bit = image->vk.format == VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16;
struct ac_video_dec_session_param param = {
.sub_sample = AC_VIDEO_SUBSAMPLE_420,
.max_width = image->vk.extent.width,
.max_height = image->vk.extent.height,
.max_bit_depth = is_10bit ? 10 : 8,
.max_num_ref = image->vk.array_layers,
};
for (uint32_t i = 0; i < profile_list->profileCount; i++) {
switch (profile_list->pProfiles[i].videoCodecOperation) {
case VK_VIDEO_CODEC_OPERATION_DECODE_H264_BIT_KHR:
param.codec = AC_VIDEO_CODEC_AVC;
break;
case VK_VIDEO_CODEC_OPERATION_DECODE_H265_BIT_KHR:
param.codec = AC_VIDEO_CODEC_HEVC;
break;
default:
UNREACHABLE("Invalid operation");
}
image->size = MAX2(image->size, ac_video_dec_dpb_size(&pdev->info, &param));
}
}
bool
radv_video_decode_vp9_supported(const struct radv_physical_device *pdev)
{

2
src/amd/vulkan/radv_video.h
View file

@ -91,6 +91,8 @@ VkResult radv_video_get_encode_session_memory_requirements(struct radv_device *d
uint32_t *pMemoryRequirementsCount,
VkVideoSessionMemoryRequirementsKHR *pMemoryRequirements);
void radv_video_patch_encode_session_parameters(struct radv_device *device, struct vk_video_session_parameters *params);
void radv_video_get_uvd_dpb_image(struct radv_physical_device *pdev,
const struct VkVideoProfileListInfoKHR *profile_list, struct radv_image *image);
void radv_video_get_enc_dpb_image(struct radv_device *device, const struct VkVideoProfileListInfoKHR *profile_list,
struct radv_image *image, struct radv_image_create_info *create_info);
bool radv_video_decode_vp9_supported(const struct radv_physical_device *pdev);