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119 commits

Author SHA1 Message Date
Marek Olšák
3d9e87406c radeonsi: fix a hang with instancing on Hawaii 
This fixes "piglit/bin/arb_transform_feedback2-draw-auto instanced".

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
 2014-07-28 23:57:08 +02:00
Marek Olšák
d808de31bd radeonsi: only update vertex buffers when they need updating 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-07-18 01:58:59 +02:00
Marek Olšák
0ed0bf0696 radeonsi: move vertex buffer descriptors from IB to memory 
This removes the intermediate storage (pm4 state) and generates descriptors
directly in a staging buffer.

It also reduces the number of flushes, because the descriptors no longer
take CS space.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-07-18 01:58:59 +02:00
Marek Olšák
2a7b57ad42 radeonsi: implement ARB_draw_indirect 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-07-18 01:58:58 +02:00
Marek Olšák
887b69a233 radeonsi: don't add info->start to the index buffer offset 
info->start will be invalid once info->indirect isn't NULL, so it shouldn't
be added to ib.offset.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-07-18 01:58:58 +02:00
Marek Olšák
09056b352d radeonsi: use an SGPR instead of VGT_INDX_OFFSET 
The draw indirect packets cannot set VGT_INDX_OFFSET, they can only set user
data SGPRs. This is the only way to support start/index_bias with indirect
drawing.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-07-18 01:58:58 +02:00
Marek Olšák
6a2b38381e radeonsi: pass ARB_conservative_depth parameters to the hardware 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-06-19 00:17:36 +02:00
Marek Olšák
d9e102b220 radeonsi: prepare depth export registers at compile time 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-05-10 13:58:46 +02:00
Marek Olšák
023d367ae6 radeonsi: remove unused variable exports_ps in si_pipe_shader_ps 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-05-10 13:58:46 +02:00
Marek Olšák
315f3c171d radeonsi: use DRAW_PREAMBLE on CIK 
It's the same as setting the 3 regs separately, but shorter, and it also
seems to be required on GFX7.2 and later. This doesn't fix Hawaii.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-05-10 13:58:46 +02:00
Adam Jackson
74388dd24b radeonsi: Don't use anonymous struct trick in atom tracking 
I'm somewhat impressed that current gccs will let you do this, but
sufficiently old ones (including 4.4.7 in RHEL6) won't.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
 2014-05-08 12:05:58 -04:00
Marek Olšák
6a5499b9d9 radeonsi: move framebuffer-related state to a new struct si_framebuffer 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-03-11 18:51:20 +01:00
Marek Olšák
bee2b96b02 r600g,radeonsi: set priorities for relocations 2014-03-11 18:51:19 +01:00
Marek Olšák
c32114460d gallium: remove PIPE_USAGE_STATIC 
Reviewed-by: Brian Paul <brianp@vmware.com>
 2014-02-06 17:37:34 +01:00
Michel Dänzer
b4e14931a9 radeonsi: Pass VS resource descriptors to the HW ES shader stage as well 
This makes sure constants and samplers work in the vertex shader even
when a geometry shader is active.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:43 +09:00
Michel Dänzer
d88a375229 radeonsi: Simplify shader PM4 state handling 
Just always bind the current states before drawing.

Besides the simplification, as a bonus this makes sure the VS hardware
shader stage always uses the GS copy shader when a geometry shader is
active, fixing a number of GS related piglit tests.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:08:21 +09:00
Michel Dänzer
8afde9fa23 radeonsi: Take GS into account for VS state in more places 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:35 +09:00
Michel Dänzer
28630713b2 radeonsi: Handle adjacency primitives 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:23 +09:00
Michel Dänzer
d8b3d806fc radeonsi: Handle TGSI_SEMANTIC_PRIMID 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:07:11 +09:00
Michel Dänzer
7c7d7380f1 radeonsi: Generalize counting of shader parameters 
Now it covers ES->GS as well as VS->PS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:06:58 +09:00
Michel Dänzer
404b29d765 radeonsi: Initial geometry shader support 
Partly based on the corresponding r600g work by Vadim Girlin and Dave
Airlie.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-29 11:06:28 +09:00
Marek Olšák
7209703432 radeonsi: cleanup includes, add missing license 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:40:13 +01:00
Marek Olšák
9f5c037ab9 radeonsi: inline si_translate_index_buffer 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:57 +01:00
Marek Olšák
0932f0ff14 radeonsi: inline si_upload_index_buffer 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:53 +01:00
Marek Olšák
a4c218f398 r600g,radeonsi: consolidate variables for CS tracing 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:42 +01:00
Marek Olšák
ba0c16f7b2 r600g,radeonsi: consolidate get_timestamp, get_driver_query_info 
This enables more queries for the Gallium HUD with radeonsi.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:39 +01:00
Marek Olšák
62d55c0a2d radeonsi: use queries from r600g 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
 2014-01-28 01:39:10 +01:00
Marek Olšák
69c29cb147 radeonsi: handle R600_CONTEXT_PS_PARTIAL_FLUSH in si_emit_cache_flush 
For consistency only, This is unused by radeonsi currently.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-01-23 01:47:14 +01:00
Andreas Hartmetz
8662e66bf2 radeonsi: Rename the commonly occurring rctx/r600 variables. 
The "r" stands for R600.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:14 +01:00
Andreas Hartmetz
44d27ce2b2 radeonsi: Rename r600_trace_emit->si_trace_emit. 
I had previously considered that unsafe.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:13 +01:00
Andreas Hartmetz
0b57fc15e1 radeonsi: Rename R600->SI in some remaining defines. 
I had previously considered that unsafe.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:13 +01:00
Andreas Hartmetz
b902298615 radeonsi: Rename r600->si remaining identifiers in si_state_draw.c. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:13 +01:00
Andreas Hartmetz
45578def71 radeonsi: Rename r600->si for functions in si_pipe.h. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:13 +01:00
Andreas Hartmetz
238aeabce0 radeonsi: Rename r600->si for structs in si_pipe.h. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:13 +01:00
Andreas Hartmetz
786af2f963 radeonsi: Apply si_* file naming scheme. 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2014-01-14 00:07:13 +01:00
Marek Olšák
1a63f278f2 radeonsi: make DB_RENDER_OVERRIDE an invariant register 
All this cruft was ported from r600g and isn't needed on SI and later
according to hw docs. If we implemented HiS, we would set it to 0.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-17 15:41:46 +01:00
Marek Olšák
249cb511c5 radeonsi: flush HTILE when appropriate 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-17 15:41:46 +01:00
Marek Olšák
2eb321b992 radeonsi: move invariant regs to si_init_config 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-14 17:42:08 +01:00
Marek Olšák
7fa8fb7382 radeonsi: fix binding the dummy pixel shader 
This fixes valgrind errors in glxinfo.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-12 18:48:04 +01:00
Marek Olšák
e9fc552837 radeonsi: remove unused variable in si_pipe_shader_ps 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-12 18:48:04 +01:00
Andreas Hartmetz
8ee7370c9b radeonsi: Write htile state to hardware. 2013-12-12 18:34:11 +01:00
Marek Olšák
d52791a708 radeonsi: add driver support for layered rendering and AMD_vertex_shader_layer 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-03 19:39:13 +01:00
Marek Olšák
053606ddae radeonsi: implement OpenGL edge flags 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-12-03 19:39:13 +01:00
Marek Olšák
e5f0080d91 radeonsi: try to fix IA_MULTI_VGT_PARAM programming 
This doesn't make any difference on Bonaire, but it might help on Hawaii.
 2013-11-04 19:07:57 +01:00
Marek Olšák
6b7c039dc2 radeonsi: fix occlusion queries for CIK 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-10-09 11:44:48 +02:00
Marek Olšák
ec922ef987 radeonsi: draw register fixes for CIK 
This doesn't fix any known issue. I'm just following the docs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-10-09 11:44:48 +02:00
Marek Olšák
09fc5d6e26 radeonsi: implement clear_buffer using CP DMA, initialize CMASK with it 
More work needs to be done for this to be entirely shared with r600g.
I'm just trying to share r600_texture.c now.

The reason I put the implementation to si_descriptors.c is that the emit
function had already been there.
 2013-09-29 15:18:09 +02:00
Marek Olšák
8d03d923b6 radeonsi: implement streamout shader support 
The shader is responsible for writing to streamout buffers using
the TBUFFER_STORE_FORMAT_* instructions.

The locations of some input SGPRs and VGPRs are assigned dynamically, because
the input SGPRs controlling streamout are not declared if they are not needed,
decreasing the indices of all following inputs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-09-13 01:04:44 +02:00
Marek Olšák
9d16e70b3f radeonsi: implement glDrawTransformFeedback functionality 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-09-13 01:04:44 +02:00
Marek Olšák
91ede46222 radeonsi: implement streamout flush properly 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2013-09-13 01:04:44 +02:00