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radeonsi: flush HTILE when appropriate
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
parent
3e2b0f801d
commit
249cb511c5
3 changed files with 8 additions and 2 deletions
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@ -197,6 +197,7 @@ void si_context_flush(struct r600_context *ctx, unsigned flags)
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ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
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R600_CONTEXT_FLUSH_AND_INV_CB_META |
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R600_CONTEXT_FLUSH_AND_INV_DB |
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R600_CONTEXT_FLUSH_AND_INV_DB_META |
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R600_CONTEXT_INV_TEX_CACHE;
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si_emit_cache_flush(&ctx->b, NULL);
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@ -2099,7 +2099,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
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R600_CONTEXT_FLUSH_AND_INV_CB_META;
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}
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if (rctx->framebuffer.zsbuf) {
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rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
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rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
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R600_CONTEXT_FLUSH_AND_INV_DB_META;
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}
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util_copy_framebuffer_state(&rctx->framebuffer, state);
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@ -676,6 +676,10 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
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}
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if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
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}
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if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
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radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
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@ -689,7 +693,7 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato
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rctx->flags = 0;
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}
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const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */
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const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
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void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
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{
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