radeonsi: flush HTILE when appropriate

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2013-12-17 00:46:45 +01:00
parent 3e2b0f801d
commit 249cb511c5
3 changed files with 8 additions and 2 deletions

View file

@ -197,6 +197,7 @@ void si_context_flush(struct r600_context *ctx, unsigned flags)
ctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
R600_CONTEXT_FLUSH_AND_INV_CB_META |
R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_DB_META |
R600_CONTEXT_INV_TEX_CACHE;
si_emit_cache_flush(&ctx->b, NULL);

View file

@ -2099,7 +2099,8 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
R600_CONTEXT_FLUSH_AND_INV_CB_META;
}
if (rctx->framebuffer.zsbuf) {
rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
R600_CONTEXT_FLUSH_AND_INV_DB_META;
}
util_copy_framebuffer_state(&rctx->framebuffer, state);

View file

@ -676,6 +676,10 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
}
if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB_META) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
}
if (rctx->flags & R600_CONTEXT_WAIT_3D_IDLE) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
@ -689,7 +693,7 @@ void si_emit_cache_flush(struct r600_common_context *rctx, struct r600_atom *ato
rctx->flags = 0;
}
const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 11 }; /* number of CS dwords */
const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /* number of CS dwords */
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
{