Commit graph

12020 commits

Author SHA1 Message Date
Lionel Landwerlin
19aeb274e6 genxml: generate opencl temporary variables with private qualifier
To avoid generic pointers, makes the NIR prints a bit more readable.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 41b2ed65 ("genxml: generate opencl packing headers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27637>
2024-02-20 14:41:43 +00:00
Lionel Landwerlin
96ab1d65cc anv: fix emission of Wa_14015055625
When moving the static part, I missed that the
pipeline->primitive_id_override field isn't set yet when we check it
to emit 3DSTATE_TE.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 1e081bd680 ("anv: split 3DSTATE_TE packing between static & dynamic parts")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27692>
2024-02-20 09:49:00 +00:00
Lionel Landwerlin
63676ed502 anv: fix Wa_16013994831 macros
The commit that switched to the WA framework forgot to update one of
the ifdef section.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: e6e320fc79 ("anv: make Wa_16013994831 to use intel_needs_workaround")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27676>
2024-02-19 12:48:33 +00:00
Lionel Landwerlin
682c23aa06 anv: remove unused definition
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Lionel Landwerlin
27a7c5447d anv: reenable ANV_ALWAYS_BINDLESS
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Lionel Landwerlin
dbee85713f anv: factor out descriptor buffer flushing
Take the opportunity to fix the flush of the descriptor buffer surface
when needed. Previously we would only flush it if the shader used one
of the push descriptor.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Lionel Landwerlin
cf193af762 anv: fixup push descriptor shader analysis
There are a couple mistakes here :

   - using a bitfield as an index to generate a bitfield...

   - in anv_nir_push_desc_ubo_fully_promoted(), confusing binding
     table access of the descriptor buffer with actual descriptors

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: ff91c5ca42 ("anv: add analysis for push descriptor uses and store it in shader cache")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27504>
2024-02-19 11:10:29 +00:00
Caio Oliveira
5feb326d80 intel/isl: Include compiler generic header
Instead of including a brw-specific one.

Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
ae50ac46d1 intel: Remove brw_ prefix from process debug function
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
c773898f39 intel/compiler: Rename brw_gfx_ver_enum.h to intel_gfx_ver_enum.h
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
d8f9a05f32 intel/compiler: Rename the passes and files related to intel_nir.h
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Caio Oliveira
dc76cfc781 intel/compiler: Collect NIR-only passes in intel_nir.h
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27644>
2024-02-16 22:35:05 +00:00
Sagar Ghuge
24db040a49 anv: Drop warnings for engine initialization failure
We don't have to spit out warnings for the end users. For compute if we
fail to initialize, we are falling back to render for compute operation,

Anyway end-user applications can query what the engines/queues are
supported based on that they can choose to use a specific queue.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27660>
2024-02-16 20:48:17 +00:00
Caio Oliveira
805d45e916 intel/decoder: Move decoder to a separate module
Depends on both intel/common and intel/compiler.  Breaks circular
dependency between these two modules.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27647>
2024-02-16 16:37:31 +00:00
José Roberto de Souza
19439624d9 anv: Use DRM_XE_VM_BIND_OP_UNMAP_ALL to unbind whole bos
For non-sparse usage there is no difference between
DRM_XE_VM_BIND_OP_UNMAP_ALL and DRM_XE_VM_BIND_OP_UNMAP but for sparse
the same bo can be bound to more than one virtual address.

Then in a case like:
img = vkCreateImage()
mem = vkAllocateMemory()
vkQueueBindSparse(img, mem)
vkFreeMemory(mem)

Note that the sparse VMA bind still points to the closed bo(done in
vkFreeMemory()), but with DRM_XE_VM_BIND_OP_UNMAP_ALL all VMAs
over the bos are removed.

Access to a unbound VMA has a defined behavior(page fault) while
access to a bound VMA without backing gem/bo don't have defined
behavior.

Suggested-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27601>
2024-02-16 13:43:45 +00:00
Mark Janes
08176d9d16 intel/tools: add shader compiler hash key to json devinfo format
Offline shader compilation will use json as the source configuration
to accurately instantiate mesa for target hardware.  Similar platforms
generate identical shader binaries even though intel_device_info
differs inconsequenially.

Include the shader compilation hash key to device info json files, so
these platforms can be deduplicated.

Closes: #6746

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:59:25 -08:00
Mark Janes
aa649dfa5f intel/tools: move intel_dev_info to intel/tools
This is a more sensible home for intel_dev_info.

Offline shader compilation will take intel_dev_info json files as
input.  For that use case, the shader compiler hash value is needed in
the json file.

intel_dev_info will depend on intel/compiler, and must be located in
intel/tools to break a circular meson dependency.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:59:15 -08:00
Mark Janes
9b1ae760a8 anv: use intel_device_info to set device UUID
For anv, use the intel device info hash function instead of
device PCI ID when generating a UUID for the pipeline cache.

PCI ID can vary between on devices which are comparable from the
perspective of the shader compiler.  A more precise key eliminates
redundant entries in a multiplatform shader cache.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:58:20 -08:00
Mark Janes
c4ce1ca847 intel/compiler: generate a hash function to use with the shader cache
Currently, Intel's shader cache incorporates PCI ID into shader cache
keys.

Many devices with different PCI IDs have identical shader compilation
functionality.  Using PCI ID as a component of the shader cache hash
means that a multi-platform shader cache will have redundant,
identical entries for similar platforms.

All Intel compiler functionality is selected based on device
configuration in `struct intel_device_info`.  intel_device_info.py
flags all fields accessed by intel/compiler.

This commit generates a hash function incorporating intel/compiler
device info fields.  Using this hash function in place of PCI ID will
produce a multiplatform cache with no duplicated content.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26844>
2024-02-15 16:58:15 -08:00
Caio Oliveira
5a88267366 intel: Add missing dependencies on blorp
Various components implicitly depend on blorp, make this explicit.

Checked by setting a 'compiler_args' on idep_intel_blorp and verifying
it on blorp_priv.h header.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27643>
2024-02-16 00:08:42 +00:00
Caio Oliveira
3b48b7df1f intel/blorp: Use a Meson dependency for blorp
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27643>
2024-02-16 00:08:42 +00:00
Sagar Ghuge
f55f9272e4 intel/compiler: Fix disassembly of URB message descriptor on Xe2+
URB messages follow the LSC message descriptor so we are already
disassembling the descriptor/extended descriptor, we don't have to
duplicate it.

Without this change:
   urb MsgDesc: ( store, a32, d32, V4, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = 8 flat )  mlen 2 ex_mlen 8 rlen 0 { align1 1H $1 };

with this change:
   urb MsgDesc: ( store, a32, d32, V4, L1UC_L3WB dst_len = 0, src0_len = 2, src1_len = 8 flat )  base_offset 0  { align1 1H $1 };

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27498>
2024-02-15 19:46:55 +00:00
Lionel Landwerlin
f733215c12 anv: enable query clear/copy using shaders on MTL/ARL
It seems like an L3 setting is different between DG2 & MTL, breaking
the L3 coherency with CS.

We can apply the same tile cache flush as we do on TGL for now until
we figure out how to configure L3 properly to avoid this.

Tested with :

 $ query_clear_with_blorp_threshold=0 query_copy_with_shader_threshold=0 ./deqp-vk -n dEQP-VK.query_pool.*

to force the shader optimizations.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27597>
2024-02-15 17:25:37 +00:00
Caio Oliveira
62a8de99ac intel/blorp: Move brw_compiler.h include to where is needed
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:19 +00:00
Caio Oliveira
f4df4be7e7 intel/blorp: Avoid brw types in blorp_priv.h
Abuse void* here so there's one less file dependent on specific brw
types.  We can revisit if there's a need later, if we ever end up with
a common type for prog_data.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:19 +00:00
Caio Oliveira
b28cf9123b intel/blorp: Move brw_blorp_get_urb_length helper
Moving to blorp_genX_exec.h to help make blorp_priv.h independent of brw
types.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:19 +00:00
Caio Oliveira
b34df9f801 intel/blorp: Remove outdated reference in comment
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:19 +00:00
Caio Oliveira
9377dc417d intel/blorp: Use a struct to return blorp_compile_*() results
Allocate the prog_data instead of expecting one from the user, also
explicitly return both kernel and prog_data size, so that the
plumbing code isn't required to use the exact prog_data type.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:19 +00:00
Caio Oliveira
82ecc219e0 intel/blorp: Simplify blorp_compile_cs() interface
No need to take brw_prog_cs_key.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:19 +00:00
Caio Oliveira
cfad85eed0 intel/blorp: Simplify blorp_compile_fs() interface
Take multisample_fbo parameter instead of a brw_wm_key.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:18 +00:00
Caio Oliveira
16ba2478fa intel/blorp: Remove brw_ prefix when not applicable
Remove the brw_ prefix from some blorp functions and structs to avoid
confusion with what's related to brw and what's not.  Some of those will
become independent of brw in upcoming patches.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:18 +00:00
Caio Oliveira
c8fda63378 intel/blorp: Don't require specific prog_data type in callback
Make interface less dependent on brw types.  If we care, later
might make sense to add a tagged union for the possible types here.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
2024-02-15 10:29:18 +00:00
Caio Oliveira
0b751a2134 intel: Rename i965_{asm,disasm} tools to brw_{asm,disasm}
And move them inside the compiler since they (especially asm) rely on
a bunch of internal types.

Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27579>
2024-02-15 09:26:46 +00:00
Caio Oliveira
5992185c8d intel/compiler: Merge intel_disasm.[ch] into corresponding brw files
Rename the functions to match the existing ones.

Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27579>
2024-02-15 09:26:46 +00:00
Caio Oliveira
468a0ffe9c intel/compiler: Include brw_disasm_info.h where its used
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27579>
2024-02-15 09:26:46 +00:00
Caio Oliveira
ff95f00883 intel/compiler: Move disassemble functions to own header file
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27579>
2024-02-15 09:26:46 +00:00
Caio Oliveira
5732c9d269 intel/compiler: Rename brw_cs_dispatch_info to intel_cs_dispatch_info
And move to the intel_shader_enums.h file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
2024-02-14 22:31:23 -08:00
Caio Oliveira
c5b80de583 intel/compiler: Rename brw_vue_map to intel_vue_map
And move to the intel_shader_enums.h file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
2024-02-14 22:31:23 -08:00
Caio Oliveira
7d85d2c7fd intel/compiler: Rename DISPATCH_MODE_* enums to INTEL_DISPATCH_MODE_*
And move to the intel_shader_enums.h file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
2024-02-14 22:31:23 -08:00
Caio Oliveira
aeda865b6d intel/compiler: Rename BRW_TESS_* enums to INTEL_TESS_*
And move to the intel_shader_enums.h file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
2024-02-14 22:31:23 -08:00
Caio Oliveira
26dd1f0bba intel/compiler: Rename BRW_WM_MSAA_* enums to INTEL_MSAA_*
And move to the intel_shader_enums.h file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
2024-02-14 22:31:23 -08:00
Caio Oliveira
a88084f8be intel/compiler: Rename brw_image_param to isl_image_param
And move them to ISL.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
2024-02-14 22:31:23 -08:00
Jordan Justen
c6e855b64b intel/compiler: Verify SIMD16 is used for xe2 BTD/RT dispatch
Ref: HSD 14011192593

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
Jordan Justen
820e04ead4 intel/compiler: Implement nir_intrinsic_load_topology_id_intel for xe2
Rework:
 * Sagar: Rework BRW_TOPOLOGY_ID_DSS, BRW_TOPOLOGY_ID_EU_THREAD_SIMD
   calculations

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
Sagar Ghuge
8f880d0ad7 intel/dev: Update max_subslices_per_slice comment
Mention that max_subslices_per_slice relates to GT_SS_PER_SLICE in SKU.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
Jordan Justen
b533bf7361 intel/compiler: Set branch shader required-width as 16 for xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
2024-02-14 20:07:13 +00:00
José Roberto de Souza
4423454daa intel/common: Implement xe_engines_is_guc_semaphore_functional()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
dff96257da intel/common: Implement i915_engines_is_guc_semaphore_functional()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
29ee85c203 anv: Use intel_engines_supported_count()
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00
José Roberto de Souza
fe2982278f intel/common: Add intel_engines_supported_count()
This function is intented to check for KMD, platform or debug options
and return the number of engines that can actually be used.

Next patches will implement i915/xe_engines_is_guc_semaphore_functional()
functions.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25233>
2024-02-14 17:29:54 +00:00