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intel/compiler: Set branch shader required-width as 16 for xe2

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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27529>
This commit is contained in:
Jordan Justen 2023-01-31 16:02:47 -08:00 • committed by Marge Bot
parent 5022e5f4bf
commit b533bf7361
1 changed files with 2 additions and 2 deletions
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4
src/intel/compiler/brw_fs.cpp
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@ -8297,9 +8297,9 @@ compile_single_bs(const struct brw_compiler *compiler,
.prog_data = prog_data,
/* Since divergence is a lot more likely in RT than compute, it makes
* sense to limit ourselves to SIMD8 for now.
* sense to limit ourselves to the smallest available SIMD for now.
*/
.required_width = 8,
.required_width = compiler->devinfo->ver >= 20 ? 16u : 8u,
};
std::unique_ptr<fs_visitor> v[2];