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intel/compiler: Rename DISPATCH_MODE_* enums to INTEL_DISPATCH_MODE_*

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And move to the intel_shader_enums.h file.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27475>
This commit is contained in:
Caio Oliveira 2024-02-01 13:58:36 -08:00
parent aeda865b6d
commit 7d85d2c7fd
16 changed files with 40 additions and 40 deletions
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4
src/intel/blorp/blorp_genX_exec.h
View file

@ -724,7 +724,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
{
struct brw_vs_prog_data *vs_prog_data = params->vs_prog_data;
assert(!vs_prog_data || GFX_VER < 11 ||
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
vs_prog_data->base.dispatch_mode == INTEL_DISPATCH_MODE_SIMD8);
blorp_emit(batch, GENX(3DSTATE_VS), vs) {
if (vs_prog_data) {
@ -742,7 +742,7 @@ blorp_emit_vs_config(struct blorp_batch *batch,
batch->blorp->isl_dev->info->max_vs_threads - 1;
assert(GFX_VER < 8 ||
vs_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
vs_prog_data->base.dispatch_mode == INTEL_DISPATCH_MODE_SIMD8);
#if GFX_VER >= 8 && GFX_VER < 20
vs.SIMD8DispatchEnable = true;
#endif

12
src/intel/compiler/brw_compiler.h
View file

@ -1475,16 +1475,6 @@ void brw_setup_vue_interpolation(const struct brw_vue_map *vue_map,
struct nir_shader *nir,
struct brw_wm_prog_data *prog_data);
enum shader_dispatch_mode {
DISPATCH_MODE_4X1_SINGLE = 0,
DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
DISPATCH_MODE_SIMD8 = 3,
DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
DISPATCH_MODE_TCS_MULTI_PATCH = 2,
};
struct brw_vue_prog_data {
struct brw_stage_prog_data base;
struct brw_vue_map vue_map;
@ -1504,7 +1494,7 @@ struct brw_vue_prog_data {
*/
unsigned urb_entry_size;
enum shader_dispatch_mode dispatch_mode;
enum intel_shader_dispatch_mode dispatch_mode;
};
struct brw_vs_prog_data {

10
src/intel/compiler/brw_fs.cpp
View file

@ -6888,13 +6888,13 @@ fs_visitor::set_tcs_invocation_id()
invocation_id = bld.vgrf(BRW_REGISTER_TYPE_UD);
if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH) {
if (vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH) {
/* gl_InvocationID is just the thread number */
bld.SHR(invocation_id, t, brw_imm_ud(instance_id_shift));
return;
}
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH);
assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH);
fs_reg channels_uw = bld.vgrf(BRW_REGISTER_TYPE_UW);
fs_reg channels_ud = bld.vgrf(BRW_REGISTER_TYPE_UD);
@ -6945,8 +6945,8 @@ fs_visitor::run_tcs()
struct brw_vue_prog_data *vue_prog_data = brw_vue_prog_data(prog_data);
const fs_builder bld = fs_builder(this).at_end();
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH ||
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH ||
vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH);
payload_ = new tcs_thread_payload(*this);
@ -6954,7 +6954,7 @@ fs_visitor::run_tcs()
set_tcs_invocation_id();
const bool fix_dispatch_mask =
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH &&
vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH &&
(nir->info.tess.tcs_vertices_out % 8) != 0;
/* Fix the disptach mask */

2
src/intel/compiler/brw_fs_nir.cpp
View file

@ -2978,7 +2978,7 @@ fs_nir_emit_tcs_intrinsic(nir_to_brw_state &ntb,
fs_inst *inst;
const bool multi_patch =
vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH;
vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH;
fs_reg icp_handle = multi_patch ?
get_tcs_multi_patch_icp_handle(ntb, bld, instr) :

4
src/intel/compiler/brw_fs_thread_payload.cpp
View file

@ -46,7 +46,7 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
struct brw_tcs_prog_data *tcs_prog_data = brw_tcs_prog_data(v.prog_data);
struct brw_tcs_prog_key *tcs_key = (struct brw_tcs_prog_key *) v.key;
if (vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_SINGLE_PATCH) {
if (vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH) {
patch_urb_output = brw_ud1_grf(0, 0);
primitive_id = brw_vec1_grf(0, 1);
@ -55,7 +55,7 @@ tcs_thread_payload::tcs_thread_payload(const fs_visitor &v)
num_regs = 5;
} else {
assert(vue_prog_data->dispatch_mode == DISPATCH_MODE_TCS_MULTI_PATCH);
assert(vue_prog_data->dispatch_mode == INTEL_DISPATCH_MODE_TCS_MULTI_PATCH);
assert(tcs_key->input_vertices <= BRW_MAX_TCS_INPUT_VERTICES);
unsigned r = 0;

2
src/intel/compiler/brw_shader.cpp
View file

@ -1387,7 +1387,7 @@ brw_compile_tes(const struct brw_compiler *compiler,
assert(v.payload().num_regs % reg_unit(devinfo) == 0);
prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo);
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
fs_generator g(compiler, &params->base,
&prog_data->base.base, false, MESA_SHADER_TESS_EVAL);

10
src/intel/compiler/brw_vec4.cpp
View file

@ -1858,13 +1858,13 @@ vec4_visitor::convert_to_hw_regs()
static bool
stage_uses_interleaved_attributes(unsigned stage,
enum shader_dispatch_mode dispatch_mode)
enum intel_shader_dispatch_mode dispatch_mode)
{
switch (stage) {
case MESA_SHADER_TESS_EVAL:
return true;
case MESA_SHADER_GEOMETRY:
return dispatch_mode != DISPATCH_MODE_4X2_DUAL_OBJECT;
return dispatch_mode != INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
default:
return false;
}
@ -1878,7 +1878,7 @@ stage_uses_interleaved_attributes(unsigned stage,
*/
static unsigned
get_lowered_simd_width(const struct intel_device_info *devinfo,
enum shader_dispatch_mode dispatch_mode,
enum intel_shader_dispatch_mode dispatch_mode,
unsigned stage, const vec4_instruction *inst)
{
/* Do not split some instructions that require special handling */
@ -2650,7 +2650,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
if (is_scalar) {
const unsigned dispatch_width = compiler->devinfo->ver >= 20 ? 16 : 8;
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
fs_visitor v(compiler, &params->base, &key->base,
&prog_data->base.base, nir, dispatch_width,
@ -2684,7 +2684,7 @@ brw_compile_vs(const struct brw_compiler *compiler,
}
if (!assembly) {
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
vec4_vs_visitor v(compiler, &params->base, key, prog_data,
nir, debug_enabled);

2
src/intel/compiler/brw_vec4_copy_propagation.cpp
View file

@ -463,7 +463,7 @@ vec4_visitor::opt_copy_propagation(bool do_constant_prop)
* to be interleaved, so one register contains two attribute slots.
*/
const int attributes_per_reg =
prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
prog_data->dispatch_mode == INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
bool progress = false;
struct copy_entry entries[alloc.total_size];

10
src/intel/compiler/brw_vec4_gs_visitor.cpp
View file

@ -132,7 +132,7 @@ vec4_gs_visitor::setup_payload()
* to be interleaved, so one register contains two attribute slots.
*/
int attributes_per_reg =
prog_data->dispatch_mode == DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
prog_data->dispatch_mode == INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT ? 1 : 2;
int reg = 0;
@ -822,7 +822,7 @@ brw_compile_gs(const struct brw_compiler *compiler,
fs_visitor v(compiler, &params->base, &c, prog_data, nir,
params->base.stats != NULL, debug_enabled);
if (v.run_gs()) {
prog_data->base.dispatch_mode = DISPATCH_MODE_SIMD8;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
assert(v.payload().num_regs % reg_unit(compiler->devinfo) == 0);
prog_data->base.base.dispatch_grf_start_reg =
@ -856,7 +856,7 @@ brw_compile_gs(const struct brw_compiler *compiler,
*/
if (prog_data->invocations <= 1 &&
!INTEL_DEBUG(DEBUG_NO_DUAL_OBJECT_GS)) {
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
brw::vec4_gs_visitor v(compiler, &params->base, &c, prog_data, nir,
true /* no_spills */,
@ -920,9 +920,9 @@ brw_compile_gs(const struct brw_compiler *compiler,
* SINGLE mode.
*/
if (prog_data->invocations <= 1 || compiler->devinfo->ver < 7)
prog_data->base.dispatch_mode = DISPATCH_MODE_4X1_SINGLE;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_4X1_SINGLE;
else
prog_data->base.dispatch_mode = DISPATCH_MODE_4X2_DUAL_INSTANCE;
prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_INSTANCE;
brw::vec4_gs_visitor *gs = NULL;
const unsigned *ret = NULL;

4
src/intel/compiler/brw_vec4_tcs.cpp
View file

@ -396,12 +396,12 @@ brw_compile_tcs(const struct brw_compiler *compiler,
prog_data->patch_count_threshold = brw::get_patch_count_threshold(key->input_vertices);
if (compiler->use_tcs_multi_patch) {
vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_MULTI_PATCH;
vue_prog_data->dispatch_mode = INTEL_DISPATCH_MODE_TCS_MULTI_PATCH;
prog_data->instances = nir->info.tess.tcs_vertices_out;
prog_data->include_primitive_id = has_primitive_id;
} else {
unsigned verts_per_thread = is_scalar ? 8 : 2;
vue_prog_data->dispatch_mode = DISPATCH_MODE_TCS_SINGLE_PATCH;
vue_prog_data->dispatch_mode = INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH;
prog_data->instances =
DIV_ROUND_UP(nir->info.tess.tcs_vertices_out, verts_per_thread);
}

10
src/intel/compiler/intel_shader_enums.h
View file

@ -76,6 +76,16 @@ enum intel_tess_domain {
};
/** @} */
enum intel_shader_dispatch_mode {
INTEL_DISPATCH_MODE_4X1_SINGLE = 0,
INTEL_DISPATCH_MODE_4X2_DUAL_INSTANCE = 1,
INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT = 2,
INTEL_DISPATCH_MODE_SIMD8 = 3,
INTEL_DISPATCH_MODE_TCS_SINGLE_PATCH = 0,
INTEL_DISPATCH_MODE_TCS_MULTI_PATCH = 2,
};
#ifdef __cplusplus
} /* extern "C" */
#endif

2
src/intel/compiler/test_vec4_cmod_propagation.cpp
View file

@ -54,7 +54,7 @@ public:
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false, false)
{
prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
prog_data->dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
}
protected:

2
src/intel/compiler/test_vec4_copy_propagation.cpp
View file

@ -50,7 +50,7 @@ public:
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false /* no_spills */, false)
{
prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
prog_data->dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
}
protected:

2
src/intel/compiler/test_vec4_dead_code_eliminate.cpp
View file

@ -50,7 +50,7 @@ public:
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false /* no_spills */, false)
{
prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
prog_data->dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
}
protected:

2
src/intel/compiler/test_vec4_register_coalesce.cpp
View file

@ -53,7 +53,7 @@ public:
: vec4_visitor(compiler, params, NULL, prog_data, shader,
false /* no_spills */, false)
{
prog_data->dispatch_mode = DISPATCH_MODE_4X2_DUAL_OBJECT;
prog_data->dispatch_mode = INTEL_DISPATCH_MODE_4X2_DUAL_OBJECT;
}
protected:

2
src/intel/vulkan/genX_pipeline.c
View file

@ -1357,7 +1357,7 @@ emit_3dstate_hs_ds(struct anv_graphics_pipeline *pipeline,
DISPATCH_MODE_SIMD8_SINGLE_PATCH :
DISPATCH_MODE_SIMD4X2;
#else
assert(tes_prog_data->base.dispatch_mode == DISPATCH_MODE_SIMD8);
assert(tes_prog_data->base.dispatch_mode == INTEL_DISPATCH_MODE_SIMD8);
ds.DispatchMode = DISPATCH_MODE_SIMD8_SINGLE_PATCH;
#endif