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intel/blorp: Remove brw_ prefix when not applicable

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Remove the brw_ prefix from some blorp functions and structs to avoid
confusion with what's related to brw and what's not.  Some of those will
become independent of brw in upcoming patches.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27581>
This commit is contained in:
Caio Oliveira 2024-01-22 21:20:52 -08:00 • committed by Marge Bot
parent c8fda63378
commit 16ba2478fa
5 changed files with 122 additions and 122 deletions
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16
src/intel/blorp/blorp.c
View file

@ -142,8 +142,8 @@ blorp_batch_finish(struct blorp_batch *batch)
}
void
brw_blorp_surface_info_init(struct blorp_batch *batch,
struct brw_blorp_surface_info *info,
blorp_surface_info_init(struct blorp_batch *batch,
struct blorp_surface_info *info,
const struct blorp_surf *surf,
unsigned int level, float layer,
enum isl_format format, bool is_dest)
@ -376,9 +376,9 @@ blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx,
NIR_PASS_V(nir, nir_lower_io, nir_var_uniform, type_size_scalar_bytes,
(nir_lower_io_options)0);
STATIC_ASSERT(offsetof(struct brw_blorp_wm_inputs, subgroup_id) + 4 ==
sizeof(struct brw_blorp_wm_inputs));
nir->num_uniforms = offsetof(struct brw_blorp_wm_inputs, subgroup_id);
STATIC_ASSERT(offsetof(struct blorp_wm_inputs, subgroup_id) + 4 ==
sizeof(struct blorp_wm_inputs));
nir->num_uniforms = offsetof(struct blorp_wm_inputs, subgroup_id);
unsigned nr_params = nir->num_uniforms / 4;
cs_prog_data->base.nr_params = nr_params;
cs_prog_data->base.param = rzalloc_array(NULL, uint32_t, nr_params);
@ -408,7 +408,7 @@ blorp_compile_cs(struct blorp_context *blorp, void *mem_ctx,
}
struct blorp_sf_key {
struct brw_blorp_base_key base;
struct blorp_base_key base;
struct brw_sf_prog_key key;
};
@ -425,7 +425,7 @@ blorp_ensure_sf_program(struct blorp_batch *batch,
return true;
struct blorp_sf_key key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_GFX4_SF),
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_GFX4_SF),
};
/* Everything gets compacted in vertex setup, so we just need a
@ -500,7 +500,7 @@ blorp_hiz_op(struct blorp_batch *batch, struct blorp_surf *surf,
for (uint32_t a = 0; a < num_layers; a++) {
const uint32_t layer = start_layer + a;
brw_blorp_surface_info_init(batch, &params.depth, surf, level,
blorp_surface_info_init(batch, &params.depth, surf, level,
layer, surf->surf->format, true);
/* Align the rectangle primitive to 8x4 pixels.

122
src/intel/blorp/blorp_blit.c
View file

@ -34,8 +34,8 @@
static const bool split_blorp_blit_debug = false;
struct brw_blorp_blit_vars {
/* Input values from brw_blorp_wm_inputs */
struct blorp_blit_vars {
/* Input values from blorp_wm_inputs */
nir_variable *v_bounds_rect;
nir_variable *v_rect_grid;
nir_variable *v_coord_transform;
@ -46,8 +46,8 @@ struct brw_blorp_blit_vars {
};
static void
brw_blorp_blit_vars_init(nir_builder *b, struct brw_blorp_blit_vars *v,
const struct brw_blorp_blit_prog_key *key)
blorp_blit_vars_init(nir_builder *b, struct blorp_blit_vars *v,
const struct blorp_blit_prog_key *key)
{
#define LOAD_INPUT(name, type)\
v->v_##name = BLORP_CREATE_NIR_INPUT(b->shader, name, type);
@ -65,8 +65,8 @@ brw_blorp_blit_vars_init(nir_builder *b, struct brw_blorp_blit_vars *v,
static nir_def *
blorp_blit_get_frag_coords(nir_builder *b,
const struct brw_blorp_blit_prog_key *key,
struct brw_blorp_blit_vars *v)
const struct blorp_blit_prog_key *key,
struct blorp_blit_vars *v)
{
nir_def *coord = nir_f2i32(b, nir_load_frag_coord(b));
@ -92,8 +92,8 @@ blorp_blit_get_frag_coords(nir_builder *b,
static nir_def *
blorp_blit_get_cs_dst_coords(nir_builder *b,
const struct brw_blorp_blit_prog_key *key,
struct brw_blorp_blit_vars *v)
const struct blorp_blit_prog_key *key,
struct blorp_blit_vars *v)
{
nir_def *coord = nir_load_global_invocation_id(b, 32);
@ -118,7 +118,7 @@ blorp_blit_get_cs_dst_coords(nir_builder *b,
*/
static nir_def *
blorp_blit_apply_transform(nir_builder *b, nir_def *src_pos,
struct brw_blorp_blit_vars *v)
struct blorp_blit_vars *v)
{
nir_def *coord_transform = nir_load_var(b, v->v_coord_transform);
@ -131,7 +131,7 @@ blorp_blit_apply_transform(nir_builder *b, nir_def *src_pos,
}
static nir_tex_instr *
blorp_create_nir_tex_instr(nir_builder *b, struct brw_blorp_blit_vars *v,
blorp_create_nir_tex_instr(nir_builder *b, struct blorp_blit_vars *v,
nir_texop op, nir_def *pos, unsigned num_srcs,
nir_alu_type dst_type)
{
@ -169,8 +169,8 @@ blorp_create_nir_tex_instr(nir_builder *b, struct brw_blorp_blit_vars *v,
}
static nir_def *
blorp_nir_tex(nir_builder *b, struct brw_blorp_blit_vars *v,
const struct brw_blorp_blit_prog_key *key, nir_def *pos)
blorp_nir_tex(nir_builder *b, struct blorp_blit_vars *v,
const struct blorp_blit_prog_key *key, nir_def *pos)
{
if (key->need_src_offset)
pos = nir_fadd(b, pos, nir_i2f32(b, nir_load_var(b, v->v_src_offset)));
@ -193,7 +193,7 @@ blorp_nir_tex(nir_builder *b, struct brw_blorp_blit_vars *v,
}
static nir_def *
blorp_nir_txf(nir_builder *b, struct brw_blorp_blit_vars *v,
blorp_nir_txf(nir_builder *b, struct blorp_blit_vars *v,
nir_def *pos, nir_alu_type dst_type)
{
nir_tex_instr *tex =
@ -208,7 +208,7 @@ blorp_nir_txf(nir_builder *b, struct brw_blorp_blit_vars *v,
}
static nir_def *
blorp_nir_txf_ms(nir_builder *b, struct brw_blorp_blit_vars *v,
blorp_nir_txf_ms(nir_builder *b, struct blorp_blit_vars *v,
nir_def *pos, nir_def *mcs, nir_alu_type dst_type)
{
nir_tex_instr *tex =
@ -235,7 +235,7 @@ blorp_nir_txf_ms(nir_builder *b, struct brw_blorp_blit_vars *v,
}
static nir_def *
blorp_blit_txf_ms_mcs(nir_builder *b, struct brw_blorp_blit_vars *v,
blorp_blit_txf_ms_mcs(nir_builder *b, struct blorp_blit_vars *v,
nir_def *pos)
{
nir_tex_instr *tex =
@ -256,7 +256,7 @@ blorp_blit_txf_ms_mcs(nir_builder *b, struct brw_blorp_blit_vars *v,
*
* (X', Y', S') = detile(W-MAJOR, tile(Y-MAJOR, X, Y, S))
*
* (See brw_blorp_build_nir_shader).
* (See blorp_build_nir_shader).
*/
static inline nir_def *
blorp_nir_retile_y_to_w(nir_builder *b, nir_def *pos)
@ -312,7 +312,7 @@ blorp_nir_retile_y_to_w(nir_builder *b, nir_def *pos)
*
* (X', Y', S') = detile(Y-MAJOR, tile(W-MAJOR, X, Y, S))
*
* (See brw_blorp_build_nir_shader).
* (See blorp_build_nir_shader).
*/
static inline nir_def *
blorp_nir_retile_w_to_y(nir_builder *b, nir_def *pos)
@ -557,7 +557,7 @@ static inline int count_trailing_one_bits(unsigned value)
}
static nir_def *
blorp_nir_combine_samples(nir_builder *b, struct brw_blorp_blit_vars *v,
blorp_nir_combine_samples(nir_builder *b, struct blorp_blit_vars *v,
nir_def *pos, unsigned tex_samples,
enum isl_aux_usage tex_aux_usage,
nir_alu_type dst_type,
@ -713,8 +713,8 @@ blorp_nir_combine_samples(nir_builder *b, struct brw_blorp_blit_vars *v,
static nir_def *
blorp_nir_manual_blend_bilinear(nir_builder *b, nir_def *pos,
unsigned tex_samples,
const struct brw_blorp_blit_prog_key *key,
struct brw_blorp_blit_vars *v)
const struct blorp_blit_prog_key *key,
struct blorp_blit_vars *v)
{
nir_def *pos_xy = nir_trim_vector(b, pos, 2);
nir_def *rect_grid = nir_load_var(b, v->v_rect_grid);
@ -859,7 +859,7 @@ blorp_nir_manual_blend_bilinear(nir_builder *b, nir_def *pos,
*/
static nir_def *
bit_cast_color(struct nir_builder *b, nir_def *color,
const struct brw_blorp_blit_prog_key *key)
const struct blorp_blit_prog_key *key)
{
if (key->src_format == key->dst_format)
return color;
@ -982,7 +982,7 @@ swizzle_color(struct nir_builder *b, nir_def *color,
static nir_def *
convert_color(struct nir_builder *b, nir_def *color,
const struct brw_blorp_blit_prog_key *key)
const struct blorp_blit_prog_key *key)
{
/* All of our color conversions end up generating a single-channel color
* value that we need to write out.
@ -1158,9 +1158,9 @@ convert_color(struct nir_builder *b, nir_def *color,
* of samples).
*/
static nir_shader *
brw_blorp_build_nir_shader(struct blorp_context *blorp,
blorp_build_nir_shader(struct blorp_context *blorp,
struct blorp_batch *batch, void *mem_ctx,
const struct brw_blorp_blit_prog_key *key)
const struct blorp_blit_prog_key *key)
{
const struct intel_device_info *devinfo = blorp->isl_dev->info;
nir_def *src_pos, *dst_pos, *color;
@ -1200,8 +1200,8 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp,
compute ? MESA_SHADER_COMPUTE : MESA_SHADER_FRAGMENT;
blorp_nir_init_shader(&b, mem_ctx, stage, NULL);
struct brw_blorp_blit_vars v;
brw_blorp_blit_vars_init(&b, &v, key);
struct blorp_blit_vars v;
blorp_blit_vars_init(&b, &v, key);
dst_pos = compute ?
blorp_blit_get_cs_dst_coords(&b, key, &v) :
@ -1498,9 +1498,9 @@ brw_blorp_build_nir_shader(struct blorp_context *blorp,
}
static bool
brw_blorp_get_blit_kernel_fs(struct blorp_batch *batch,
struct blorp_params *params,
const struct brw_blorp_blit_prog_key *key)
blorp_get_blit_kernel_fs(struct blorp_batch *batch,
struct blorp_params *params,
const struct blorp_blit_prog_key *key)
{
struct blorp_context *blorp = batch->blorp;
@ -1513,7 +1513,7 @@ brw_blorp_get_blit_kernel_fs(struct blorp_batch *batch,
const unsigned *program;
struct brw_wm_prog_data prog_data;
nir_shader *nir = brw_blorp_build_nir_shader(blorp, batch, mem_ctx, key);
nir_shader *nir = blorp_build_nir_shader(blorp, batch, mem_ctx, key);
nir->info.name =
ralloc_strdup(nir, blorp_shader_type_to_name(key->base.shader_type));
@ -1536,9 +1536,9 @@ brw_blorp_get_blit_kernel_fs(struct blorp_batch *batch,
}
static bool
brw_blorp_get_blit_kernel_cs(struct blorp_batch *batch,
struct blorp_params *params,
const struct brw_blorp_blit_prog_key *prog_key)
blorp_get_blit_kernel_cs(struct blorp_batch *batch,
struct blorp_params *params,
const struct blorp_blit_prog_key *prog_key)
{
struct blorp_context *blorp = batch->blorp;
@ -1551,7 +1551,7 @@ brw_blorp_get_blit_kernel_cs(struct blorp_batch *batch,
const unsigned *program;
struct brw_cs_prog_data prog_data;
nir_shader *nir = brw_blorp_build_nir_shader(blorp, batch, mem_ctx,
nir_shader *nir = blorp_build_nir_shader(blorp, batch, mem_ctx,
prog_key);
nir->info.name = ralloc_strdup(nir, "BLORP-gpgpu-blit");
blorp_set_cs_dims(nir, prog_key->local_y);
@ -1574,10 +1574,10 @@ brw_blorp_get_blit_kernel_cs(struct blorp_batch *batch,
}
static void
brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform,
float src0, float src1,
float dst0, float dst1,
bool mirror)
blorp_setup_coord_transform(struct blorp_coord_transform *xform,
float src0, float src1,
float dst0, float dst1,
bool mirror)
{
double scale = (double)(src1 - src0) / (double)(dst1 - dst0);
if (!mirror) {
@ -1605,7 +1605,7 @@ brw_blorp_setup_coord_transform(struct brw_blorp_coord_transform *xform,
}
static inline void
surf_get_intratile_offset_px(struct brw_blorp_surface_info *info,
surf_get_intratile_offset_px(struct blorp_surface_info *info,
uint32_t *tile_x_px, uint32_t *tile_y_px)
{
if (info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED) {
@ -1623,7 +1623,7 @@ surf_get_intratile_offset_px(struct brw_blorp_surface_info *info,
void
blorp_surf_convert_to_single_slice(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info)
struct blorp_surface_info *info)
{
bool ok UNUSED;
@ -1677,7 +1677,7 @@ blorp_surf_convert_to_single_slice(const struct isl_device *isl_dev,
void
blorp_surf_fake_interleaved_msaa(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info)
struct blorp_surface_info *info)
{
assert(info->surf.msaa_layout == ISL_MSAA_LAYOUT_INTERLEAVED);
@ -1691,7 +1691,7 @@ blorp_surf_fake_interleaved_msaa(const struct isl_device *isl_dev,
void
blorp_surf_retile_w_to_y(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info)
struct blorp_surface_info *info)
{
assert(info->surf.tiling == ISL_TILING_W);
@ -1731,7 +1731,7 @@ blorp_surf_retile_w_to_y(const struct isl_device *isl_dev,
}
static bool
can_shrink_surface(const struct brw_blorp_surface_info *surf)
can_shrink_surface(const struct blorp_surface_info *surf)
{
/* The current code doesn't support offsets into the aux buffers. This
* should be possible, but we need to make sure the offset is page
@ -1756,7 +1756,7 @@ can_shrink_surface(const struct brw_blorp_surface_info *surf)
static unsigned
get_max_surface_size(const struct intel_device_info *devinfo,
const struct brw_blorp_surface_info *surf)
const struct blorp_surface_info *surf)
{
const unsigned max = devinfo->ver >= 7 ? 16384 : 8192;
if (split_blorp_blit_debug && can_shrink_surface(surf))
@ -1826,7 +1826,7 @@ get_red_format_for_rgb_format(enum isl_format format)
void
surf_fake_rgb_with_red(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info)
struct blorp_surface_info *info)
{
blorp_surf_convert_to_single_slice(isl_dev, info);
@ -1872,7 +1872,7 @@ enum blit_shrink_status {
static enum blit_shrink_status
try_blorp_blit(struct blorp_batch *batch,
struct blorp_params *params,
struct brw_blorp_blit_prog_key *key,
struct blorp_blit_prog_key *key,
struct blt_coords *coords)
{
const struct intel_device_info *devinfo = batch->blorp->isl_dev->info;
@ -1929,11 +1929,11 @@ try_blorp_blit(struct blorp_batch *batch,
params->x1 = params->wm_inputs.bounds_rect.x1 = round(coords->x.dst1);
params->y1 = params->wm_inputs.bounds_rect.y1 = round(coords->y.dst1);
brw_blorp_setup_coord_transform(&params->wm_inputs.coord_transform[0],
blorp_setup_coord_transform(&params->wm_inputs.coord_transform[0],
coords->x.src0, coords->x.src1,
coords->x.dst0, coords->x.dst1,
coords->x.mirror);
brw_blorp_setup_coord_transform(&params->wm_inputs.coord_transform[1],
blorp_setup_coord_transform(&params->wm_inputs.coord_transform[1],
coords->y.src0, coords->y.src1,
coords->y.dst0, coords->y.dst1,
coords->y.mirror);
@ -2203,10 +2203,10 @@ try_blorp_blit(struct blorp_batch *batch,
}
if (compute) {
if (!brw_blorp_get_blit_kernel_cs(batch, params, key))
if (!blorp_get_blit_kernel_cs(batch, params, key))
return 0;
} else {
if (!brw_blorp_get_blit_kernel_fs(batch, params, key))
if (!blorp_get_blit_kernel_fs(batch, params, key))
return 0;
if (!blorp_ensure_sf_program(batch, params))
@ -2274,7 +2274,7 @@ get_px_size_sa(const struct isl_surf *surf)
static void
shrink_surface_params(const struct isl_device *dev,
struct brw_blorp_surface_info *info,
struct blorp_surface_info *info,
double *x0, double *x1, double *y0, double *y1)
{
uint64_t offset_B;
@ -2328,7 +2328,7 @@ shrink_surface_params(const struct isl_device *dev,
static void
do_blorp_blit(struct blorp_batch *batch,
const struct blorp_params *orig_params,
struct brw_blorp_blit_prog_key *key,
struct blorp_blit_prog_key *key,
const struct blt_coords *orig)
{
struct blorp_params params;
@ -2538,9 +2538,9 @@ blorp_blit(struct blorp_batch *batch,
}
}
brw_blorp_surface_info_init(batch, &params.src, src_surf, src_level,
blorp_surface_info_init(batch, &params.src, src_surf, src_level,
src_layer, src_format, false);
brw_blorp_surface_info_init(batch, &params.dst, dst_surf, dst_level,
blorp_surface_info_init(batch, &params.dst, dst_surf, dst_level,
dst_layer, dst_format, true);
params.src.view.swizzle = src_swizzle;
@ -2549,8 +2549,8 @@ blorp_blit(struct blorp_batch *batch,
const struct isl_format_layout *src_fmtl =
isl_format_get_layout(params.src.view.format);
struct brw_blorp_blit_prog_key key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_BLIT),
struct blorp_blit_prog_key key = {
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_BLIT),
.base.shader_pipeline = compute ? BLORP_SHADER_PIPELINE_COMPUTE :
BLORP_SHADER_PIPELINE_RENDER,
.filter = filter,
@ -2785,7 +2785,7 @@ get_ccs_compatible_copy_format(const struct isl_format_layout *fmtl)
void
blorp_surf_convert_to_uncompressed(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info,
struct blorp_surface_info *info,
uint32_t *x, uint32_t *y,
uint32_t *width, uint32_t *height)
{
@ -2947,13 +2947,13 @@ blorp_copy(struct blorp_batch *batch,
dst_surf->aux_usage));
}
brw_blorp_surface_info_init(batch, &params.src, src_surf, src_level,
blorp_surface_info_init(batch, &params.src, src_surf, src_level,
src_layer, ISL_FORMAT_UNSUPPORTED, false);
brw_blorp_surface_info_init(batch, &params.dst, dst_surf, dst_level,
blorp_surface_info_init(batch, &params.dst, dst_surf, dst_level,
dst_layer, ISL_FORMAT_UNSUPPORTED, true);
struct brw_blorp_blit_prog_key key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_COPY),
struct blorp_blit_prog_key key = {
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_COPY),
.base.shader_pipeline = compute ? BLORP_SHADER_PIPELINE_COMPUTE :
BLORP_SHADER_PIPELINE_RENDER,
.filter = BLORP_FILTER_NONE,

44
src/intel/blorp/blorp_clear.c
View file

@ -36,9 +36,9 @@
#define FILE_DEBUG_FLAG DEBUG_BLORP
#pragma pack(push, 1)
struct brw_blorp_const_color_prog_key
struct blorp_const_color_prog_key
{
struct brw_blorp_base_key base;
struct blorp_base_key base;
bool use_simd16_replicated_data;
bool clear_rgb_as_red;
uint8_t local_y;
@ -53,8 +53,8 @@ blorp_params_get_clear_kernel_fs(struct blorp_batch *batch,
{
struct blorp_context *blorp = batch->blorp;
const struct brw_blorp_const_color_prog_key blorp_key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_CLEAR),
const struct blorp_const_color_prog_key blorp_key = {
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_CLEAR),
.base.shader_pipeline = BLORP_SHADER_PIPELINE_RENDER,
.use_simd16_replicated_data = use_replicated_data,
.clear_rgb_as_red = clear_rgb_as_red,
@ -116,8 +116,8 @@ blorp_params_get_clear_kernel_cs(struct blorp_batch *batch,
{
struct blorp_context *blorp = batch->blorp;
const struct brw_blorp_const_color_prog_key blorp_key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_CLEAR),
const struct blorp_const_color_prog_key blorp_key = {
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_CLEAR),
.base.shader_pipeline = BLORP_SHADER_PIPELINE_COMPUTE,
.use_simd16_replicated_data = false,
.clear_rgb_as_red = clear_rgb_as_red,
@ -202,7 +202,7 @@ blorp_params_get_clear_kernel(struct blorp_batch *batch,
#pragma pack(push, 1)
struct layer_offset_vs_key {
struct brw_blorp_base_key base;
struct blorp_base_key base;
unsigned num_inputs;
};
#pragma pack(pop)
@ -220,7 +220,7 @@ blorp_params_get_layer_offset_vs(struct blorp_batch *batch,
{
struct blorp_context *blorp = batch->blorp;
struct layer_offset_vs_key blorp_key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_LAYER_OFFSET_VS),
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_LAYER_OFFSET_VS),
};
if (params->wm_prog_data)
@ -468,7 +468,7 @@ blorp_fast_clear(struct blorp_batch *batch,
if (!blorp_params_get_clear_kernel(batch, &params, true, false))
return;
brw_blorp_surface_info_init(batch, &params.dst, surf, level,
blorp_surface_info_init(batch, &params.dst, surf, level,
start_layer, format, true);
params.num_samples = params.dst.surf.samples;
@ -635,7 +635,7 @@ blorp_clear(struct blorp_batch *batch,
return;
while (num_layers > 0) {
brw_blorp_surface_info_init(batch, &params.dst, surf, level,
blorp_surface_info_init(batch, &params.dst, surf, level,
start_layer, format, true);
params.dst.view.swizzle = swizzle;
@ -820,7 +820,7 @@ blorp_clear_stencil_as_rgba(struct blorp_batch *batch,
for (uint32_t a = 0; a < num_layers; a++) {
uint32_t layer = start_layer + a;
brw_blorp_surface_info_init(batch, &params.dst, surf, level,
blorp_surface_info_init(batch, &params.dst, surf, level,
layer, ISL_FORMAT_UNSUPPORTED, true);
if (surf->surf->samples > 1)
@ -891,7 +891,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch,
params.num_layers = num_layers;
if (stencil_mask) {
brw_blorp_surface_info_init(batch, &params.stencil, stencil,
blorp_surface_info_init(batch, &params.stencil, stencil,
level, start_layer,
ISL_FORMAT_UNSUPPORTED, true);
params.stencil_mask = stencil_mask;
@ -913,7 +913,7 @@ blorp_clear_depth_stencil(struct blorp_batch *batch,
}
if (clear_depth) {
brw_blorp_surface_info_init(batch, &params.depth, depth,
blorp_surface_info_init(batch, &params.depth, depth,
level, start_layer,
ISL_FORMAT_UNSUPPORTED, true);
params.z = depth_value;
@ -1078,7 +1078,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
for (uint32_t l = 0; l < num_layers; l++) {
const uint32_t layer = start_layer + l;
if (clear_stencil) {
brw_blorp_surface_info_init(batch, &params.stencil, stencil,
blorp_surface_info_init(batch, &params.stencil, stencil,
level, layer,
ISL_FORMAT_UNSUPPORTED, true);
params.stencil_mask = 0xff;
@ -1090,7 +1090,7 @@ blorp_hiz_clear_depth_stencil(struct blorp_batch *batch,
/* If we're clearing depth, we must have HiZ */
assert(depth && isl_aux_usage_has_hiz(depth->aux_usage));
brw_blorp_surface_info_init(batch, &params.depth, depth,
blorp_surface_info_init(batch, &params.depth, depth,
level, layer,
ISL_FORMAT_UNSUPPORTED, true);
params.depth.clear_color.f32[0] = depth_value;
@ -1235,7 +1235,7 @@ blorp_ccs_resolve(struct blorp_batch *batch,
default:
assert(false);
}
brw_blorp_surface_info_init(batch, &params.dst, surf,
blorp_surface_info_init(batch, &params.dst, surf,
level, start_layer, format, true);
params.x0 = params.y0 = 0;
@ -1326,7 +1326,7 @@ blorp_nir_bit(nir_builder *b, nir_def *src, unsigned bit)
#pragma pack(push, 1)
struct blorp_mcs_partial_resolve_key
{
struct brw_blorp_base_key base;
struct blorp_base_key base;
bool indirect_clear_color;
bool int_format;
uint32_t num_samples;
@ -1339,7 +1339,7 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
{
struct blorp_context *blorp = batch->blorp;
const struct blorp_mcs_partial_resolve_key blorp_key = {
.base = BRW_BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE),
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE),
.indirect_clear_color = params->dst.clear_color_addr.buffer != NULL,
.int_format = isl_format_has_int_channel(params->dst.view.format),
.num_samples = params->num_samples,
@ -1423,9 +1423,9 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
params.x1 = surf->surf->logical_level0_px.width;
params.y1 = surf->surf->logical_level0_px.height;
brw_blorp_surface_info_init(batch, &params.src, surf, 0,
blorp_surface_info_init(batch, &params.src, surf, 0,
start_layer, format, false);
brw_blorp_surface_info_init(batch, &params.dst, surf, 0,
blorp_surface_info_init(batch, &params.dst, surf, 0,
start_layer, format, true);
params.num_samples = params.dst.surf.samples;
@ -1498,7 +1498,7 @@ blorp_mcs_ambiguate(struct blorp_batch *batch,
default: unreachable("Unexpected MCS format size for ambiguate");
}
params.dst = (struct brw_blorp_surface_info) {
params.dst = (struct blorp_surface_info) {
.enabled = true,
.surf = *surf->aux_surf,
.addr = surf->aux_addr,
@ -1558,7 +1558,7 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
isl_format_get_layout(surf->aux_surf->format);
assert(aux_fmtl->txc == ISL_TXC_CCS);
params.dst = (struct brw_blorp_surface_info) {
params.dst = (struct blorp_surface_info) {
.enabled = true,
.addr = surf->aux_addr,
.view = {

10
src/intel/blorp/blorp_genX_exec.h
View file

@ -1497,7 +1497,7 @@ blorp_emit_memcpy(struct blorp_batch *batch,
static void
blorp_emit_surface_state(struct blorp_batch *batch,
const struct brw_blorp_surface_info *surface,
const struct blorp_surface_info *surface,
UNUSED enum isl_aux_op aux_op,
void *state, uint32_t state_offset,
uint8_t color_write_disable,
@ -1596,7 +1596,7 @@ blorp_emit_surface_state(struct blorp_batch *batch,
static void
blorp_emit_null_surface_state(struct blorp_batch *batch,
const struct brw_blorp_surface_info *surface,
const struct blorp_surface_info *surface,
uint32_t *state)
{
struct GENX(RENDER_SURFACE_STATE) ss = {
@ -1656,7 +1656,7 @@ blorp_setup_binding_table(struct blorp_batch *batch,
params->color_write_disable, true);
} else {
assert(params->depth.enabled || params->stencil.enabled);
const struct brw_blorp_surface_info *surface =
const struct blorp_surface_info *surface =
params->depth.enabled ? &params->depth : &params->stencil;
blorp_emit_null_surface_state(batch, surface,
surface_maps[BLORP_RENDERBUFFER_BT_INDEX]);
@ -1921,7 +1921,7 @@ blorp_emit_gfx8_hiz_op(struct blorp_batch *batch,
static void
blorp_update_clear_color(UNUSED struct blorp_batch *batch,
const struct brw_blorp_surface_info *info)
const struct blorp_surface_info *info)
{
assert(info->clear_color_addr.buffer != NULL);
#if GFX_VER == 11
@ -2409,7 +2409,7 @@ xy_bcb_surf_depth(const struct isl_surf *surf)
}
static uint32_t
xy_aux_mode(const struct brw_blorp_surface_info *info)
xy_aux_mode(const struct blorp_surface_info *info)
{
switch (info->aux_usage) {
case ISL_AUX_USAGE_CCS_E:

52
src/intel/blorp/blorp_priv.h
View file

@ -47,7 +47,7 @@ enum {
#define BLORP_SAMPLER_INDEX 0
struct brw_blorp_surface_info
struct blorp_surface_info
{
bool enabled;
@ -70,31 +70,31 @@ struct brw_blorp_surface_info
};
void
brw_blorp_surface_info_init(struct blorp_batch *batch,
struct brw_blorp_surface_info *info,
blorp_surface_info_init(struct blorp_batch *batch,
struct blorp_surface_info *info,
const struct blorp_surf *surf,
unsigned int level, float layer,
enum isl_format format, bool is_dest);
void
blorp_surf_convert_to_single_slice(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info);
struct blorp_surface_info *info);
void
surf_fake_rgb_with_red(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info);
struct blorp_surface_info *info);
void
blorp_surf_convert_to_uncompressed(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info,
struct blorp_surface_info *info,
uint32_t *x, uint32_t *y,
uint32_t *width, uint32_t *height);
void
blorp_surf_fake_interleaved_msaa(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info);
struct blorp_surface_info *info);
void
blorp_surf_retile_w_to_y(const struct isl_device *isl_dev,
struct brw_blorp_surface_info *info);
struct blorp_surface_info *info);
struct brw_blorp_coord_transform
struct blorp_coord_transform
{
float multiplier;
float offset;
@ -110,7 +110,7 @@ struct brw_blorp_coord_transform
*
* See blorp_check_in_bounds().
*/
struct brw_blorp_bounds_rect
struct blorp_bounds_rect
{
uint32_t x0;
uint32_t x1;
@ -122,7 +122,7 @@ struct brw_blorp_bounds_rect
* Grid needed for blended and scaled blits of integer formats, see
* blorp_nir_manual_blend_bilinear().
*/
struct brw_blorp_rect_grid
struct blorp_rect_grid
{
float x1;
float y1;
@ -134,13 +134,13 @@ struct blorp_surf_offset {
uint32_t y;
};
struct brw_blorp_wm_inputs
struct blorp_wm_inputs
{
uint32_t clear_color[4];
struct brw_blorp_bounds_rect bounds_rect;
struct brw_blorp_rect_grid rect_grid;
struct brw_blorp_coord_transform coord_transform[2];
struct blorp_bounds_rect bounds_rect;
struct blorp_rect_grid rect_grid;
struct blorp_coord_transform coord_transform[2];
struct blorp_surf_offset src_offset;
struct blorp_surf_offset dst_offset;
@ -183,7 +183,7 @@ blorp_create_nir_input(struct nir_shader *nir,
#define BLORP_CREATE_NIR_INPUT(shader, name, type) \
blorp_create_nir_input((shader), #name, (type), \
offsetof(struct brw_blorp_wm_inputs, name))
offsetof(struct blorp_wm_inputs, name))
struct blorp_vs_inputs {
uint32_t base_layer;
@ -228,16 +228,16 @@ struct blorp_params
float z;
uint8_t stencil_mask;
uint8_t stencil_ref;
struct brw_blorp_surface_info depth;
struct brw_blorp_surface_info stencil;
struct blorp_surface_info depth;
struct blorp_surface_info stencil;
uint32_t depth_format;
struct brw_blorp_surface_info src;
struct brw_blorp_surface_info dst;
struct blorp_surface_info src;
struct blorp_surface_info dst;
enum isl_aux_op hiz_op;
bool full_surface_hiz_op;
enum isl_aux_op fast_clear_op;
uint8_t color_write_disable;
struct brw_blorp_wm_inputs wm_inputs;
struct blorp_wm_inputs wm_inputs;
struct blorp_vs_inputs vs_inputs;
bool dst_clear_color_as_input;
unsigned num_samples;
@ -265,23 +265,23 @@ const char *blorp_op_to_name(enum blorp_op op);
void blorp_params_init(struct blorp_params *params);
struct brw_blorp_base_key
struct blorp_base_key
{
char name[8];
enum blorp_shader_type shader_type;
enum blorp_shader_pipeline shader_pipeline;
};
#define BRW_BLORP_BASE_KEY_INIT(_type) \
(struct brw_blorp_base_key) { \
#define BLORP_BASE_KEY_INIT(_type) \
(struct blorp_base_key) { \
.name = "blorp", \
.shader_type = _type, \
.shader_pipeline = BLORP_SHADER_PIPELINE_RENDER, \
}
struct brw_blorp_blit_prog_key
struct blorp_blit_prog_key
{
struct brw_blorp_base_key base;
struct blorp_base_key base;
/* Number of samples per pixel that have been configured in the surface
* state for texturing from.